University of Minnesota
Institute of Technology
myU OneStop

Electrical and Computer Engineering

Implementing Successive Approximation A/D Converters in Sub-65nm CMOS Technologies

Prof. Richard Carley
Carnegie Mellon University

In the early days of MOS integrated circuits (way back in the 1970's), getting any kind of accurate analog-to-digital converter (ADC) to work was very challenging.  Designers only had depletion-mode and enhancement-mode NMOS transistors to work with; and, getting even modest analog voltage gain was quite difficult.  The successive approximation ADC, which does not require an amplifier of any kind, emerged as an important ADC architecture in these early days of MOS.  Then, as CMOS took hold in the 1980's, many other ADC architectures took over and successive approximation became just one of many possible choices.

As CMOS process technology scales to gate lengths of 45nm and below, achieving analog voltage gain is again becoming a major challenge.  In part, the more three dimensional nature of very short channel MOSFETs results in drain induced barrier lowering that typically drops the gain of a single transistor amplifier down into the 5-10X  range.  Further, because the power supply voltages have dropped down under 1V,  adding cascode transistors to increase voltage gain is difficult.  In this talk, the impressive capabilities of successive approximation ADC architectures implemented in sub-65nm CMOS technologies will be reviewed. This talk will review some of the circuit and architecture "tricks" that can improve the match between the requirements of successive approximation ADCs and the capabilities of sub-65nm CMOS technologies. Two  very different 45nm CMOS ADC designs that were recently developed at Carnegie Mellon will be described.  The first ADC adopts digital error correction techniques to increase the accuracy of the basic successive approximation ADC to over 11 bits.  The second ADC to be described develops strategies for achieving extremely high sampling rates (over 2GS/s) using time interleaving of successive approximation ADCs.

Short Biography: L. Richard Carley received an S.B. in 1976, an M.S. in 1978, and a Ph.D. in 1984, all from the Massachusetts Institute of Technology.  He joined Carnegie Mellon University in Pittsburgh Pennsylvania in 1984, and in March 2001, he became the STMicroelectronics Professor of Engineering at CMU.  Dr. Carley’s research interests include analog and RF integrated circuit design in deeply scaled CMOS technologies and novel nano-electro-mechanical device design and fabrication.  Dr. Carley has been granted 15 patents, authored or co-authored over 120 technical papers, and authored or co-authored over 20 books and/or book chapters.  He has won numerous awards including Best Technical Paper Awards at both the 1987 and the 2002 Design Automation Conference (DAC).  In 1997, Dr. Carley co-founded the analog electronic design automation startup, Neolinear, which became part of Cadence in 2004.  In 2001, Dr. Carley co-founded a MEMS sensor IC startup which morphed into a MEMS RF IC startup in 2005 and then ceased operations in 2008 due to turmoil in the financial markets.