Pavan Kumar Hanumolu, Ph.D.
Oregon State University
Clock generation, distribution, and recovery are essential in all integrated systems.
Almost all the clock generation and recovery techniques of the past several decades are
based on phase-locked loop(PLL) techniques. However, shrinking supply voltages, increasing
leakage, and poor analog performance of the transistor in modern day CMOS processes make
the design of high-performance PLLs to generate high-fidelity clocks extremely challenging.
The need for integrating PLLs in a large system-on-a-chip further exacerbate these issues.
This talk will first highlight the design challenges and will present emerging design paradigms
to combat the aforementioned challenges. Specifically, digital techniques to enhance the
performance of analog PLLs and architectures to mitigate both intrinsic (thermal and flicker)
and extrinsic (supply) noise sources will be discussed.
Pavan Hanumolu received the Ph.D. degree in electrical engineering from Oregon State
University in 2006. Currently, he is an Assistant Professor in the school of Electrical
Engineering and Computer Science at the same University. His research interests
include high-speed I/O interfaces, digital techniques to compensate for analog circuit
imperfections, time-based signal processing, and power-management circuits.