Prof. Janet Meiling Wang-Roveda
University of Arizona
Growing variability has been observed in nanometer CMOS due to limits in design and manufacture technology. The resulting diminished accuracy has caused a significant reduction in the parametric yield. In the presence of significant variations, the worst-case-based analysis is too pessimistic and the simulation based sampling schemes require excessive computation time due to the large parametric space. A new self-tuning design is proposed to sense and tune circuit performance on the fly. The proposed design stores a set of functions that model variability using probability collocation approach. Through delay difference, the self-tuning design adjusts voltages among different VLSI components. On the other side, the probability collocation approach significantly reduces turnaround time for the pre-silicon stage, and provides accurate full chip verification down to 40nm technology. The presentation addresses a range of other designs that have been developed by Dr. Roveda’s group: the fast, compressed data processing system for breast cancer detection and the secured data transmission for cloud computing. Looking forward, we focus our efforts on the designs of bio-medical circuits and systems to facilitate early and smart detection. Additional comments on present efforts in yeast circuit designs will conclude the discussion.
Janet Roveda received a B.S. degree in Computer Science from The East China Institute in 1991, M.S., and Ph.D. degrees in Electrical Engineering and Computer Sciences from the University of California, Berkeley in 1998 and 2000, respectively. She was a recipient of the NSF career award and the PEACASE award in 2005 and 2006, respectively. She received the best paper award in ISQED 2010 as well as best paper nominations in ASPDAC 2010, ICCAD 2007, and ISQED 2005. She is the recipient of the 2008 R. Newton Graduate Research Project Award from DAC, and the 2007 USS University of Arizona Outstanding Achievement Award. Her primary research interests focus on robust VLSI circuit design, biomedical instrument design, Smart grid, VLSI circuit modeling and analysis, and low power multi-core system design.