University of Minnesota
Institute of Technology
myU OneStop

Kia Bazargan 2013

Kia  Bazargan
Associate Professor


Area of expertise: Computer-aided Design of VLSI circuits,
CAD for FPGA, FPGA architecture, reconfigurable computing

Ph.D., 2000, Northwestern University, Evanston, IL, United States
M.S., 1998, Northwestern University, Evanston, IL, United States
B.S., CS, 1996, Sharif University of Technology, Tehran, Iran

Contact information
Office: 4-159 Keller Hall
Telephone: (612) 625-4588
E-mail: kia (at)
Personal Web Site

National Science Foundation CAREER award, 2003

My research interests are primarily in the field of VLSI-CAD. They include FPGA physical design, reconfigurable computing, and ASIC floorplanning/placement. I do some FPGA designs as well.

Advances in the FPGA technology have made them increasingly more powerful in the past decade, and their market share is increasing every year. The main reason for their popularity is their flexibility in changing designs without having to go through more fabrication cycles. However, the performance, power, and area efficiency of FPGAs lags behind their ASIC counterparts. My objective is to bridge the gap between ASICs and FPGAs by devising better architectures, CAD algorithms, and programming paradigms.

Selected publications
Satish Sivaswamy and Kia Bazargan, "Statistics Analysis and Process Variation-Aware Routing and Skew Assignment for FPGAs", ACM Transactions on Reconfigurable Technology and Systems, Vol. 1, No 1, pp. 1-35, Mar 2008.

Wang, Gang, Satish Sivaswamy, Cristinel Ababei, Kia Bazargan, Ryan Kastner, and Eli Bozorgzadeh. "Statistical Analysis and Design of HARP Routing Pattern FPGAs". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), to appear.

Ababei, Cristinel, Yan Feng, Brent Goplan, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, and Sachin S. Sapatnekar. "Placement and Routing in 3-D Integrated Circuits". IEEE Design and Test, 22.6 (Nov.-Dec. 2005): 520-531.

Maidee, Pongstorn, Cristinel Ababei, and Kia Bazargan. "Timing-driven Partitioning-based Placement for Island Style FPGAs". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 24.3 (March 2005): 395-406.