Office: 4-163 Keller Hall
Email: jsartori (at) umn.edu
Web site: http://www.ece.umn.edu/users/jsartori
Area of Expertise
Computer Architecture, Computer-Aided Design, Stochastic Computing, Low-Power Design and Architecture, Application-aware Design
Ph.D. Electrical and Computer Engineering (2012) University of Illinois at Urbana-Champaign
M.S. Electrical and Computer Engineering (2010) University of Illinois at Urbana-Champaign
B.S. Electrical Engineering (2006) University of North Dakota, Grand Forks
Honors / Awards
Intel Computer Engineering Fellowship
Best Paper Award Nomination – HPCA 2012
Best Paper Award – CASES 2011
The underlying theme of my research has been to lay out a path into the future that allows us to continue to reap the benefits of Moore’s law. Toward this goal, my approach has been twofold. First, identify and address the primary bottlenecks that prevent the continuation of benefits from Moore’s law. Second, identify and address the disconnects between current hardware design and architecture methodologies and the computational usage models of the future.
John Sartori and Rakesh Kumar. “Branch and Data Herding: Reducing Control and Memory Divergence for Error-tolerant GPU Applications” IEEE Transactions on Multimedia (TMM) Special Issue on New Software / Hardware Paradigms for Error-tolerant Multimedia Systems, 2012.
John Sartori and Rakesh Kumar. “Exploiting Timing Error Resilience in Processor Architecture”. ACM Transactions on Embedded Computing Systems (TECS) Special Issue on Probabilistic Embedded Computing, 2012.
Andrew Kahng, Seokhyeong Kang, Rakesh Kumar, and John Sartori. “Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors”. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2012.
John Sartori and Rakesh Kumar. “Compiling for Energy Efficiency on Timing Speculative Processors”. 49th ACM/IEEE Design Automation Conference (DAC), 2012.
Joseph Sloan, John Sartori, and Rakesh Kumar. “Exploiting Application-Level Error Tolerance in Software Design for Stochastic Processors”. [Invited] 49th ACM/IEEE Design Automation Conference (DAC), 2012.
John Sartori, Ben Ahrens, and Rakesh Kumar. “Power Balanced Pipelines”. [Best Paper Award Nomination] 18th IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2012.
John Sartori and Rakesh Kumar. “Architecting Processors to Allow Voltage/Reliability Tradeoffs”. [Best Paper Award] International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES), 2011.
Rakesh Kumar, John Sartori, and Benjamin Ahrens. "Power Balanced Pipelines". U.S. Provisional Patent 61/552,703, filed October 28, 2011.