Area of expertise: Micro- and nanoelectronics, optoelectronic devices, photovoltaics,
energy harvesting, and biomedical devices
Ph.D., Electrical & Computer Engineering, 1995, University of California, Santa Barbara, CA, USA
M.S., Electrical Engineering, 1991, University of Notre Dame, Notre Dame, IN, USA
B.S., Electrical Engineering, 1989, University of Notre Dame, Notre Dame, IN, USA
6-117 Keller Hall
E-mail: skoester (at) umn.edu
Research Web site: http://www.ece.umn.edu/users/skoester
10 IBM Patent Plateau Awards
Device Research Conference Technical Program Committee (2006-2009), Conference General Chair in 2009
Keynote Speaker at 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT 2009)
Served on numerous conference organizing/technical program committees
My research goal is to develop semiconductor device solutions to address the worldwide energy crisis, and to
explore new applications for semiconductor and solid-state devices.
On the demand-side of the energy crisis, computational systems now use a significant fraction of the world-wide
energy supply, and the demand for computational resources continues to increase rapidly. To address this problem,
I am studying novel steep-subthreshold-slope transistors that could dramatically improve the efficiency of binary logic
operations compared to conventional MOSFETs. I am also interested in photonic interconnects and customized
hybrid Si/III-V 3D integrated systems that could reduce the power consumed in the communication subsystem
of computers by orders of magnitude.
I am also interested in addressing the supply side of the energy problem by exploring green power generation
technology, particularly solar cells. Nanowire-based photovoltaic systems are particularly interesting in that they
have the potential to overcome the cost/efficiency conundrum of current solar cell technology. Devices and systems
that can directly convert ambient (optical, vibrational, thermal) energy into electricity are also interesting, as they
could enable new application areas by allowing computational systems access to new environments, particularly ones
where supplying power from the grid or batteries is not practical. Such applications include remote sensing
systems and in vivo biomedical devices.
L. Chang, D. J. Frank, R. Montoye, S. J. Koester, B. Ji, P. Coteus, R. Dennard, and W. Haensch, “Practical
strategies for power-efficient computing technologies,” to be published in Proc. IEEE 98, 2010.
S. O. Koswatta, S. J. Koester, and W. Haensch, “1D broken-gap tunnel transistor with MOSFET-like
on-currents and sub-60mV/dec subthreshold swing,” Proceedings of the 2009 International Electron Devices
Meeting, Baltimore, MD, Dec. 14-16, 2009.
D. Kim, Y. Lee, D. Sylvester, D. Blaauw, Y. Lee, J. Cai, I. Lauer, L. Chang and S. J. Koester, “Heterojunction
tunneling transistor (HETT)-based extremely low power applications,” 2009 International Symposium on Low
Power Electronics and Design (ISLPED), San Francisco, CA, Aug. 19-21, 2009.
S. J. Koester, A. M. Young, R. R. Yu, S. Purushothaman, K. N. Chen, D. C. La Tulipe, N. Rana, L. Shi, M. R.
Wordeman, and E. J. Sprogis, “Wafer-level three-dimensional integration technology,” IBM J. Res. Dev. 52,
F. Liu, R. R. Yu, A. M. Young, J. P. Doyle, X. Wang, L. Shi, K.-N. Chen, X. Li, D. A. Dipaola, D. Brown, C. T.
Ryan, J. A.Hagan, K. H. Wong, M. Lu, X. Gu, N. R. Klymko, E. D. Perfecto, A. G. Merryman, K. A. Kelly, S.
Purushothaman,S. J. Koester, R. Wisnieff, and W. Haensch, “A 300-mm wafer-level three-dimensional integration
scheme using tungsten through-silicon via and hybrid Cu-adhesive bonding,” IEDM Tech. Digest, 599-602 (2008),
Proceedings of the 2008 International Electron Devices Meeting, San Francisco, CA, Dec. 15-17, 2008.
S. W. Bedell, A. Majumdar, J. A. Ott, J. Arnold, K. Fogel, S. J. Koester, and D. K. Sadana, “Mobility scaling in
short-channel length strained Ge-on-insulator P-MOSFETs,” IEEE Elect. Dev. Lett. 29, 811-3 (2008).
Y. Sun, E. W. Kiewra, S. J. Koester, N. Ruiz, A. Callegari, K. E. Fogel, D. K. Sadana, J. Fompeyrine,
D. J. Webb, J.-P.Locquet, M. Sousa, R. Germann, K. T. Shiu, and S. R. Forrest, “Enhancement-mode
buried-channel In0.7 Ga0.3 As/In0.52 Al0.48 As MOSFETs with high-k gate dielectrics,” IEEE
Elect. Dev. Lett. 28, 473-5 (2007).
S. J. Koester, C. L. Schow, L. Schares, G. Dehlinger, J. D. Schaub, F. E. Doany, and R. A. John,
“Ge-on-SOI-detector/Si-CMOS-amplifier receivers for high-performance optical communications applications,”
IEEE J. Lightwave Tech. 25, 46-57(2007).
S. J. Koester, J. D. Schaub, G. Dehlinger, and J. O. Chu, “Ge-on-SOI infrared detectors for integrated photonic
applications,”IEEE J. Sel. Top. Quant. Electron. 12, 1489-1502 (2006).
S. J. Koester, E. W. Kiewra, Y. Sun, D. A. Neumayer, J. A. Ott, M. Copel, D. K. Sadana, D. J. Webb,
J. Fompeyrine, J.-P. Locquet, C. Marchiori, M. Sousa, and R. Germann, “Evidence of electron and hole
inversion in GaAs MOS capacitors with HfO2 gate dielectrics and a-Si/SiO2 interlayers, ” Appl. Phys.
Lett. 89, 042104-1-3 (2006).
S. J. Koester, K. L. Saenger, J. O. Chu, Q. C. Ouyang, J. A. Ott, K. A. Jenkins, D. F. Canaperi, J. A. Tornello,
C. V.Jahnes, and S. E. Steen, “Laterally-scaled Si/Si0.7 Ge0.3 n-MODFETs with fmax > 200 GHz and
low operating bias,” IEEE Elect. Dev. Lett. 26, 178-80 (2005).
K. Rim, S. Koester, M. Hargrove, J. Chu, P. M. Mooney, J. Ott, T. Kanarsky, P. Ronsheim, M. Ieong, A. Grill,
and H.-S. P.Wong, “Strained Si NMOSFETs for high performance CMOS technology,” Proceedings of the 2001
Symposium on VLSI Technology, Kyoto, Japan, Jun. 12-14, 2001.