RESEARCH INTERESTS

The International Technology Roadmap for Semiconductors (ITRS) has projected that by the year 2014, 2- 5 billion transistors with 10-13nm physical gate length will be integrated on a 500-700mm2 chip using a high-volume manufacturing process. Scaling of silicon MOS transistors in the nanometer dimension will continue to trouble designers with issues such as leakage power, statistical variability, power delivery, interconnect, reliability, testing, quantum effects, etc. Yet unknown problems will arise as researchers seek for solutions to continue the historical rate of progress. Numerous research opportunities at all levels of design (software, system, architecture, circuit, device, CAD, assembly, etc) will offer innovative solutions to extend Moore¡¯s law beyond 2010. Our research team's effort focuses in the cooperative field of circuit/device and circuit/architecture for solving issues with designing high performance, low power VLSI systems in the nanometer regime.


PROJECTS

Circuit/Architecture/Device Co-Optimization for Nanoscale VLSI Systems
Scaling has made a transistor virtually free in terms of cost and area. Designers have more freedom than ever to integrate complex functions in a single package under given power constraint. However, optimizing one building block for power and performance may not yield optimal results in others. As a simple example, datapath units prefer a low Vdd and low Vt for low dynamic power whereas memory elements require a higher Vdd and higher Vt to maintain functionality and suppress leakage. Accordingly, a discrepancy exists in the direction of optimization within a single integrated system. I would like to explore device, circuit and architecture solutions to achieve the best performance and power in future integrated systems consisting of heterogeneous components with different design roadmaps.

Low-Cost Testing of High Speed Nano-Circuits Using On-Chip Sensors
Testing of high speed circuits in sub-100nm has become extremely challenging as the circuit performance surpasses the testability of the equipments. Embedding small on-chip testers that can test and diagnose the system can significantly reduce the testing cost. Also, on-chip sensors for measuring delay, supply droop and leakage variation are needed to assist the designers in making proper decisions at the circuit and architecture level. In my thesis work, I have designed a high resolution on-die leakage sensor in a nanoscale technology for measuring both intra-die and inter-die parameter variations. I would like to extend this work by continuing research on low-cost on-chip sensors for multi-parameter (delay, leakage, droop, temperature, etc.) testing of nanoscale circuits.

Design for Emerging Applications
New applications that can exploit innovative nanoscale technologies will be sought such as ubiquitous computing, sensor networks, biochips, health care, artificial organs, haptic interface, etc. Emerging applications will provide new ideas and concepts in the design paradigm. Working in the biomedical engineering field during my Master¡¯s has helped me develop an insight on how semiconductor IC technology can be applied to bio-technology. I strongly believe that looking at both the underlying nanoscale technology and the higher level application will lead to a series of collaborative research opportunities.

Computation with Non-Silicon Devices
Molecular FETs and carbon nanotube FETs are being extensively studied as possible successors to traditional CMOS. As years of experience and infrastructure development have made silicon MOSFETs what they are today, an enormous amount of time and effort will be required for the next paradigm shift. I intend to investigate the implication of non-silicon devices on future design of VLSI systems and explore new circuit techniques and architectures suitable for these structures.