VLSI Speech
and Image Coders
Our research efforts in
this area are directed towards achieving pipelining and parallel processing
in encoders and decoders used for speech and image processing applications.
The processing of high-definition and super high-definition television
video signals requires very high data rates. It is necessary to design
encoder and decoder algorithms which can be pipelined or processed in parallel.
When implemented using dedicated VLSI processors or parallel processors,
these concurrent algorithms can meet the demands of the high-throughput
real-time signal and image processing applications. We have addressed design
of high-speed algorithms for predictive coders (including differential
pulse code modulation (DPCM), and adaptive DPCM), Huffman and arithmetic
decoders, Viterbi decoders (which are variations of dynamic programming
computations), arithmetic coders, decision feedback equalizers (DFEs),
and adaptive DFEs. The research papers which describe Adaptive DPCM and
adaptive DFEs have been listed under "VLSI Digital Filters" category.
We have also developed
a number of architectures for VLSI discrete wavelet transforms which require
fewer number of registers. The number of registers have been minimized
using life time analysis. In addition, we have shown that use of a paraunitary
QMF lattice structure in a discrete wavelet transform leads to about fifty
percent reduction in hardware area at the expense of an increase in the
latency. Various approaches to implementations of DCTs have also been
compared. An approach to arbitrarily parallel
Variable Length Coder has been developed. This coder
architecture accommodates inter-symbol parallelism
in an arbitrary manner.
Selected
Publications
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K.K. Parhi, "Pipelining In Dynamic Programming Architectures", IEEE
Trans. on Signal Processing, Vol. 39, No. 6, June 1991, pp.
1442-1450.
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K.K. Parhi, "High-Speed VLSI Architectures for Huffman and Viterbi Decoders",
IEEE Trans. on Circuits and Systems, Part II: Analog and Digital Signal
Processing, Vol. 39, No. 6, June 1992, pp. 385-391.
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K.K. Parhi, and T. Nishitani, "VLSI Architectures for Discrete Wavelet
Transforms", IEEE Trans. on VLSI Systems, 1(2), June 1993,
pp. 191-202.
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T.C. Denk and K.K. Parhi, "VLSI Architectures for Lattice Structure Based
Orthonormal Discrete Wavelet Transforms", IEEE Transactions on Circuits
and Systems, Part - II: Analog and Digital Signal Processing, 44(2),
pp. 129-132, Feb. 1997
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B. Fu and K.K. Parhi, "Generalized Multiplication Free Arithmetic Codes",
IEEE Transactions on Communications, 45(5), pp. 497-501,
May 1997
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K.K. Parhi, "Parallel Processing and Pipelining in Huffman Decoder", (Chapter
12) in VLSI Implementations for Image Communications, Series Advances
in Image Communications (Edited by Peter Pirsch), Vol. 2, Elsevier
Science Publisher, Amsterdam, 1993, pp. 365-395.
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G. Shrimali, and K.K. Parhi, "Fast Arithmetic Decoder Architectures", Proceedings
of Sixth SIAM Conference on Parallel Processing for Scientific Computing,
March 22-24, 1993, Norfolk, VA, pp. 1025-1032.
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G. Shrimali, and K.K. Parhi, "Fast Arithmetic Coder Architectures", in
Proc. of the 1993 IEEE Int. Conf. on Acoustics, Speech, and Signal Processing,
April 1993, Minneapolis (MN), pp. I-361-364.
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G. Shrimali, and K.K. Parhi, "High-Speed Arithmetic Decoder Architectures",
in Proc. of the IEEE Int. Conference on Communications, May 23-26,
1993, Geneva (Switzerland), pp. 222-226.
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T.C. Denk, and K.K. Parhi, "Calculation of Minimum Number of Registers
in 2-D Discrete Wavelet Transforms using Lapped Block Processing", Proc.
of 1994 IEEE Int. Symp. on Circuits and Systems, pp. 3.77-3.80, May
30 - June 2, 1994, London.
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T.C. Denk, and K.K. Parhi, "Architectures for Lattice Structure Based Orthonormal
Discrete Wavelet Transforms", Proc. of the 1994 Int. Conf. on Application
Specific Array Processors, pp. 259-270, San Francisco, August 1994.
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M.E. Zervakis, V. Sundararajan and K.K. Parhi, "A Wavelet-Domain Algorithm
for Denoising in the Presence of Noise Outliers", Proc. of IEEE Int.
Conf. on Image Processing, pp. I-632-I-635, Santa Barbara, October
26-29, 1997
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V. Sundararajan, M.E. Zervakis and K.K. Parhi, "Area/Power Efficient Implementation
of a Wavelet Domain Robust Image Denoising System", Proc. of IEEE
Workshop on Non-Linear Signal Processing, Michigan, September 1997
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T.C. Denk and K.K. Parhi, Systolic VLSI Architectures for 1-D Discrete
Wavelet Transforms", Proc. of 1998 Asilomar Conf. on Signals, Systems
and Computers}, Nov. 1-4, 1998, Pacific Grove (CA)
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B. Fu and K.K. Parhi, "Two VLSI Design Advances in Arithmetic Coding",
Proc. of the 1995 IEEE Int. Symp. on Circuits and Systems, pp. 437-440,
Seattle (May 1995).
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R. Freking and K.K. Parhi, "An Unrestrictedly Parallel Scheme for
Ultra-High-Rate Reprogrammable Huffman Coding",
Proc. of the 1998 IEEE Int. Conf. on Acoustics, Speech
and Signal Processing, Phoenix, March 1998.
[Bac
k page] [Prof.
Parhi's homepage]