Welcome to the home page describing our research and development of a new programmable digital signal processor based on digit-serial architectures. Under the same contract, we are also investigating and developing a digit-serial reconfigurable architecture optimized for digital signal processing applications and coprocessors compatible with the digit-serial processor. This research is being conducted at the University of Minnesota and is jointly supervised by Professor Keshab K. Parhi and Professor Gerald E. Sobelman. Any and all comments and questions can be forwarded to Professor Parhi:

Yun-Nan Chang (Ph.D./RA)

Jun Ma (Ph.D./RA)

Martin Kuhlmann (Ph.D./RA)

Zhongfeng Wang (Ph.D./RA)

Zhipei Chi (Ph.D./RA)

Dhiraj Kumar (M.S./RA)

Ru-Guang Chen (M.S./RA)

Hanho Lee (Ph.D./RA)

Lijun Gao (Ph.D./RA)