Digital Integrated Circuit Chips

At Minnesota, we have already demonstrated implementation of two fine-grain pipelined chips, one for a 16x16-bit multiplier which makes use of internal redundant number representation, and another one for a 100 MHz ADPCM video codec. We have also implemented a shared divider/square-root chip and a bit-level pipelined RLS adaptive filter based on our proposed STAR (Scaled TAngent Rotation) algorithm.

Current research includes implementation of a Viterbi coder chip, another shared divider/square-root and CORDIC chips.
 

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Selected Publications

• K.K. Parhi, and M. Hatamian, "A High Sample Rate Recursive Filter Chip", in VLSI Signal Processing III, chapter 1, IEEE Press, (Proc. of the Third IEEE VLSI Signal Processing Workshop), Monterey, CA, Nov. 1988, pp. 3-14.

 
• N.R. Shanbhag, and K.K. Parhi, "VLSI Implementation of a 100 MHz Pipelined ADPCM Codec Chip", in VLSI Signal Processing VI, IEEE Press, Oct. 1993 (Proc. of the sixth IEEE VLSI Signal Processing Workshop, Veldhoven, Netherlands), pp. 114-122.

 
• M. Hatamian and K.K. Parhi, "An 85-MHz Fourth-Order Programmable IIR Digital Filter Chip", IEEE Journal of Solid State Circuits, Vol. 27, No. 2, February 1992, pp. 175-183.

 
• W. Amendola, Jr., H.R. Srinivas, and K.K. Parhi, "A 16-Bit X 16-Bit 1.2 Micron CMOS Multiplier Chip with Low Latency Vector Merging", Proc. of the 8th Int. Conf. on VLSI Design, pp. 398-402, IEEE Computer Society Press, Jan. 4-7, 1995, New Delhi, India.

 
• K.J. Raghunath and K.K. Parhi, "A 100 MHz RLS Adaptive Filter Chip", in Proc. of the IEEE Int. Conf. on Acoustics, Speech, and Signal Processing, pp. 3187-3190, May 1995, Detroit (Michigan).

 
• H.R. Srinivas and K.K. Parhi, "A Floating Point Radix-2 Shared Division/Square Root Chip", Proc. of the 1995 Int. Conf. on Computer Design, October 1995, pp. 472-478.