Low Power DSP
System Design
We have developed a two-level
hierarchical tool referred to as HEAT tool for estimation of power consumption
in datapaths. This tool has been used to estimate power consumption of
various adders, multipliers, and complex building blocks such as DCTs.
Power estimation for DSP circuits based on switching activity estimation
which incorporates glitching and correlation has also been studied.
Various approaches
to low-power arithmetic implementations are being addressed. A theoretical
approach to power estimation in binary adders based on closed form expressions
have been developed. A theoretical approach to estimation of power consumption
of multipliers has also been developed. A new type of low-power binary
adder referred to as CSMT (carry-select modified tree) adder has been developed;
this adder has less power consumption than carry-select and binary tree
adders. Various division, square-root and CORDIC architectures are being
evaluated for low-power consumption.
Approaches to power
reduction in parallel FIR filters through novel strength reduction approaches
are being studied.
A novel divided bit-line
approach has been developed for low-power implementation
of static RAMs.
Novel approaches to
power reduction by gate resizing, supply voltage scheduling
and threshold voltage scheduling are being studied based on
use of retiming approaches.
Various low-power DSP
system design approaches by pipelining of DSP structures or novel arithmetic
architectures are discussed in VLSI Digital Filters and Binary and Finite
Field Arithmetic categories.
Selected
Publications
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K.K. Parhi, VLSI Digital
Signal Processing Systems: Design and Implementation, Wiley, NY 1999
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K.K.
Parhi and F. Catthoor, "Design of High-Performance DSP Systems", Chapter
in Emerging Technologies: Designing Low-Power Digital Systems ,
Edited by R. Cavin and W. Liu, pp. 447-507, IEEE Press (ISCAS-96 Tutorial
Book)
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K.K.
Parhi, "Low-Power Digital VLSI Approaches", Chapter in Circuits and
Systems in the Information Age , Edited by Y. Huang and C. Wei, pp.
3-22, IEEE Press, June 1997 (ISCAS-97 Tutorial Book)
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J.H.
Satyanarayana and K.K. Parhi, "A Theoretical Approach to Estimation of
Bounds on Power Consumption in Digital Multipliers", IEEE Transactions
on Circuits and Systems, Part II: Analog and Digital Signal Processing,
44(6), pp. 473-481, June 1997
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J.H.
Satyanarayana and K.K. Parhi, "Theoretical Analysis of Word-Level
Switching Activity in the Presence of Glitching and Correlation",
Proc. of 9th Great Lakes Symp. on VLSI,
Ann Arbor, MI, March 1999
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D.A.
Parker and K.K. Parhi, "Low Area/Power Parallel FIR Digital Filter Implementations",
Journal of VLSI Signal Processing, 17(1), pp. 75-92, Sept.
1997
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Y.-N.
Chang, J.H. Satyanarayana and K.K. Parhi, "Systematic Design of High-Speed
and Low-Power Digit-Serial Multipliers", IEEE Trans. on
Circuits and Systems, Part II: Analog and Digital Signal Processing,
to appear
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J. Satyanarayana and K.K.
Parhi, "HEAT: Hierarchical Energy Analysis Tool", Proc. of ACM\/IEEE
Design Automation Conference , Las Vegas, pp. 9-14, June 3-7, 1996
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C. Xu, C.-Y. Wang and
K.K. Parhi, "Order-Conf igurable Programmable Power Efficient FIR Filters",
Proc. of 3rd Int. Workshop on Image and Signal Processing , pp.
535-538, November 1996, UMIST (UK) ( Invited Talk )
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K.K. Parhi, "Fast Low-Energy
VLSI Binary Addition", Proc. of IEEE Conf. on Computer Design ,
pp. 676-684, Austin, October 12-15, 1997
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W. Freking and K.K. Parhi,
"Low-Power Digital Filters using Residue Arithmetic", Proc. of 1997
Asilomar Conf. on Signals, Systems and Computers , pp. 739-743, November
1997 Invited Talk
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L. Song, K.K. Parhi, I.
Kuroda, and T. Nishitani, "Low-energy Heterogeneous Digit-Serial Reed-Solomon
Codecs", in Proc. of IEEE Int. Conf. on Acoustics, Speech and Signal
Processing , pp. 3049-3052, May 1998, Seattle
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L. Song, K.K. Parhi, I.
Kuroda and T. Nishitani, "Low-Energy Programmable Finite Field Datapath
Architectures", Proc. of IEEE Int. Symp. on Circuits and Systems
, pp. II-406-II-409, Monterey, May 31 - June 3, 1998
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R. Freking and K.K. Parhi,
"Theretical Estimation of Power Consumption in Binary Adders", Proc.
of IEEE Int. Symp. on Circuits and Systems , pp. II-453-II-457, Monterey,
May 31 - June 3, 1998
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M. Kuhlmann and K.K. Parhi,
"Power Comparison of SRT and NST Dividers", Proc. of the SPIE Advanced
Signal Processing Algorithms, Architectures, and Implementations VIII,
1998 Int. Symp. on Optical Sci., Eng. and Instrumentation , July 19-24,
1998, San Diego (CA)
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L. Song and K.K. Parhi,
"Scheduling Stragegies for Low-Energy Programmable Digit-Serial Reed-Solomon
Codecs", Proc. of 1998 IEEE Workshop on Signal Processing Systems: Design
and Implementations (SiPS) , Oct. 8-10, 1998, Boston
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M. Kuhlmann and K.K. Parhi,
"Fast Low-Power Shared Division and Sqaure-Root Architecture", Proc.
of 1998 IEEE Int. Conf. on Computer Design , Austin, Oct. 1998
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A. Karandikar and K.K.
Parhi, "Low-Power SRAM Design Using Hierarchical Divided Bit-Line Approach",
Proc. of 1998 IEEE Int. Conf. on Computer Design , Austin, Oct.
1998
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A. Shalash and K.K. Parhi,
"Power Efficient FIR Folding Transformation for Wireline Digital Communications",
Proc. of 1998 Asilomar Conf. on Signals, Systems and Computers ,
Nov. 1-4, 1998, Pacific Grove (CA)
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M. Kuhlmann and K.K. Parhi,
"Power Comparison of Flow-Graph and Distributed Arithmetic Based DCTs",
Proc. of 1998 Asilomar Conf. on Signals, Systems and Computers ,
Nov. 1-4, 1998, Pacific Grove (CA)
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H. Suzuki, Y.N. Chang
and K.K. Parhi, "Performance Tradeoffs in Digit-Serial DSP Systems", Proc.
of 1998 Asilomar Conf. on Signals, Systems and Computers , Nov. 1-4,
1998, Pacific Grove (CA)
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V. Sundararajan and
K.K. Parhi, "Low-Power Buffer Resizing of Combinational Circuits
by Buffer Redistribution", Proc. of 1999 Advanced Research on
Conf. on VLSI, March 1999
[Bac
k page] [Prof.
Parhi's homepage]