Kiarash Bazargan
Assistant Professor

B.S., 1996, Computer Science, Sharif University of Technology, Tehran, Iran.
M.S., 1998, Electrical and Computer Engineering, Northwestern University.
Ph.D., 2000, Electrical and Computer Engineering, Northwestern University.

Telephone: 612-625-4588
Office Hours

E-mail: kia@ece.umn.edu
Web Page: http://www.ece.umn.edu/users/kia/

My research interests are primarily in the field of VLSI-CAD. They include reconfigurable computing, hardware/software co-design, FPGA physical design and fast ASIC floorplanning.

Advances in the FPGA technology, both in terms of device capacity and architecture, have resulted in introduction of reconfigurable computing machines, where the hardware "adapts" itself to the running application to gain speedup. The FPGA can be used as a co-processor that can be configured to perform hardware functions customized to a given application. Hence the FPGA can be viewed as a "hardware cache".

My objective in reconfigurable computing and hardware/software co-design is to bridge the gap between the compiler front-end and the synthesis tools on the back-end. This will result in faster convergence to a better design, as well as reliable estimates to the designers in the higher levels of the design process. My approach is to provide the higher levels of the design with reliable predictions of the outcome of the back-end stages. To accurately predict quality metrics of the final steps of the design, we need to have very fast approximation methods and heuristics. That leads to my other research interests which are FPGA physical design and fast ASIC floorplanning.


Selected publications

"An Algorithmic Floorplan Predictor", A. Ranjan, K. Bazargan and M. Sarrafzadeh, IEEE Transactions on Very Large Scale Integration (VLSI) Systems

"3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems", K. Bazargan, R. Kastner and M. Sarrafzadeh, Design Automation for Embedded Systems (DAfES) - RSP1999 Special Issue, April 2000.

"Fast Template Placement for Reconfigurable Computing Systems", K. Bazargan, R. Kastner and M. Sarrafzadeh, IEEE Design and Test - Special Issue on Reconfigurable Computing, pp 68-82, January-March 2000.

"Nostradamus: A Floorplanner of Uncertain Designs", K. Bazargan, S. Kim and M. Sarrafzadeh, IEEE Transactions on Computer Aided Design, pp. 389-397, April 1999.