Larry L. Kinney
Professor
Director of Undergraduate Studies

B.S., 1964, University of Iowa
M.S., 1965, University of Iowa
Ph.D., 1968, EE, University of Iowa

Telephone: (612) 625-4359
E-mail: kinney@ece.umn.edu
Web Page: http://www.ece.umn.edu/users/kinney/


My research concerns digital system and digital computer design. Specifically, I am interested in concurrent error detection techniques, testing of logic and design for testability, distributed computer systems, computer architecture, error detecting/correcting codes, and applications of microprocessors.

Research on concurrent error detection techniques focuses on the concept of a monitor operating in parallel with the checked circuit. Evaluating different schemes and finding new techniques for application of codes has also been part of our work.

Testing research includes test vector generation, addition of logic to very large-scale integrated circuits for self-testing, and the design of (VLSI) computer architectures applicable to high-speed generation of test vectors.

Distributed computer systems and computer architecture work has included throughput analysis, system design, special purpose processors, parallel processors, and VLSI-based systems.


Selected Publications

"Extension of Critical Path Tracing", with T. Ramakrishnan, 27th ACM/IEEE Design Automation Conf., June 24-28, 1990.

"Evaluation of a Concurrent Fault Detection Method for Microprogrammed Control Units", with A. Bailas, 21st Annual International Workshop on Microprocessing and Microarchitecture, Nov. 29-Dec. 2, 1988.

"The Honeywell PI-Bux System Interface", and et al, GOMAC-88, November 1988.

"Distributed Termination on a Mesh", with J.Song, 1988 International Conference on Parallel Processing, Aug. 15-18, 1988.

"Error Detection with Latency in Sequential Circuits", with L.P. Holmquist, International Test Conference, pp. 926-933, Sept. 12-14, 1988.

"Fault Collapsing for Concurrent Error Detection Analysis", with T. Ramakrishnan, 26th Annual Allerton Conference on Comm., Cont. and Computing, Sept. 28-30, 1988.

"C-Testability of Two-Dimensional Iterative Arrays", with H. Elhuni and A. Vergis, IEEE Trans. on Computer-Aided Design of Integrated Circuits, Vol. CAD-5, No. 4, pp. 573-581, Oct. 1986.

"Concurrent Fault Detection in Microprogrammed Control Units", with S. Vijay Iyengar, IEEE Trans on Computers, Vol. C-34, no. 9, pp. 810-821, Sept. 1985.