Keshab K. Parhi
Professor

B.Tech., 1982, Indian Institute of Technology, Kharagpur
M.S.E.E., 1984, University of Pennsylvania
Ph.D., 1988, University of California, Berkeley


E-mail: parhi@ece.umn.edu
Web Page: http://www.ece.umn.edu/users/parhi/

Editor, Journal of VLSI Signal Processing
Assoc. Editor, IEEE Trans. on Signal Processing, IEEE Circuits and Systems Trans., Part-II
Former Assoc. Editor, IEEE Circuits and Systems Trans.
IEEE Browder Thompson Prize Paper Award (1991)
IEEE SP Paper Award (1991), IEEE CAS Guillemin-Cauer Award (1993)
IEEE CAS Darlington award (1994), Fellow, IEEE


I am currently pursuing research on all aspects of VLSI signal and image processing starting from algorithm and architecture design to design of digital integrated circuits and computer aided design tools. Our emphasis is on developing techniques to design architectures and algorithms which can be operateds with higher speed, or lower area or power. Different applications impose different speed-power demands on implementations of an identical algorithm. While video and radar applications require high-speed, wireless and personal communications systems applications require low-power implementations. In addition to studying VLSI implementation styles, we are also studying computer arithmetic implementations and design of CAD tools for high-level synthesis of digital signal processing (DSP) systems and for multiprocessor prototyping and task scheduling of software programmable DSP systems using data-flow graph models. See the personal web page for more details.


Selected Publications

K.K. Parhi, "Algorithm Transformation Techniques for Concurrent Processors", Proceedings of the IEEE, Special Issue on Supercomputer Technology, Vol. 77(12), December 1989, pp. 1879-1895

K.K. Parhi, and D.G. Messerschmitt, "Static Rate-Optimal Scheduling of Iterative Data Flow Programs via Optimum Unfolding", IEEE Trans. on Computers, Vol. 40(2), February 1991, pp. 178-195

M. Hatamian and K.K. Parhi, "An 85-MHz Fourth-Order Programmable IIR Digital Filter Chip", IEEE Journal of Solid State Circuits, Vol. 27, No. 2, February 1992, pp. 175-183

K.K. Parhi, "Systematic Synthesis of DSP Data Format Converters using Life-Time Analysis and Forward-Backward Register Allocation", IEEE Trans. on Circuits and Systems, Part II: Analog and Digital Signal Processing, Vol. 39, No. 7, July 1992, pp. 423-440

K.K. Parhi, and T. Nishitani, "VLSI Architectures for Discrete Wavelet Transforms", IEEE Trans. on VLSI Systems, 1(2), June 1993, pp. 191-202