EE Faculty

B.Tech., 1987, Electrical Engineering, Indian Institute of Technology, Bombay
M.S., 1989, Computer Engineering, Syracuse University
Ph.D., 1992, Electrical Engineering, University of Illinois at Urbana-Champaign

Telephone: (612) 625-0025
Office Hours

E-mail: sachin@ece.umn.edu
Web Page: http://www.ece.umn.edu/users/sachin/

My research is primarily in the area of computer-aided design (CAD) of VLSI systems. Industry roadmaps show that at least until the year 2010 (and most likely, well beyond), silicon feature sizes will continue to shrink, the transistor count in chips will continue to increase, and performance requirements will become increasingly stringent. Under such a scenario, CAD techniques are essential for the design of high-performance circuits. The research in our group is centered around design automation for optimization and analysis, concentrating on timing, power and layout issues. Some specific problems that we have worked on in the recent past include retiming, clock skew optimization, interconnect optimization, transistor sizing, and symbolic analysis. Our focus has been on being able to build practical algorithms that can provide accurate solutions with a reasonable amount of computation.

Selected publications

Random Walks in a Supply Network, Proceedings of the ACM/IEEE Design Automation Conference, pp. 93 - 98, 2003, H. Qian, S. R. Nassif and S. S. Sapatnekar

Standby Power Optimization via Transistor Sizing and Dual Threshold Voltage Assignment, Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 375 - 378, 2002, M. Ketkar and S. S. Sapatnekar

Optimal Decoupling Capacitor Sizing and Placement for Standard Cell Layout Designs, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 4, April 2003. H. Su, S. S. Sapatnekar, and S. R. Nassif

Fast On-Chip Inductance Simulation using a Precorrected-FFT Method, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 1, pp. 49 - 61, January 2003, H. Hu, D. T. Blaauw, V. Zolotov, K. Gala, M. Zhao, R. Panda, and S. S. Sapatnekar

A Timing-constrained Simultaneous Global Routing Algorithm, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 9, pp. 1025 - 1036, September 2002, J. Hu and S. S. Sapatnekar