Faculty Directory
Keshab K. Parhi
Professor
Education
- Ph.D., 1988, University of California, Berkeley, CA, United States
- M.S., EE, 1984, University of Pennsylvania, Philadelphia, PA, United States
- B.Tech., 1982, Indian Institute of Technology, Kharagpur, India
Contact Information
- 6-181 EECS
- Telephone: (612) 624-4116
- E-mail: parhi
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- Personal Web Site
Honors/Awards
- Editor, Journal of VLSI Signal Processing
- Assoc. Editor, IEEE Transactions on Signal Processing, IEEE Circuits and Systems Transactions, Part II
- Former Assoc. Editor, IEEE Circuits and Systems Transactions
Synopsis
I am currently pursuing research on all aspects of VLSI signal and image processing starting from algorithm and architecture design to design of digital integrated circuits and computer-aided design tools. Our emphasis is on developing techniques to design architectures and algorithms which can be operated with high speed, or lower area or power. Different applications impose different speed-power demands on implementations of an identical algorithm. While video and radar applications require high-speed, wireless and personal communications systems applications require low-power implementations. In addition to studying VLSI implementation styles, we are also studying computer arithmetic implementations and design of CAD tools for high-level synthesis of digital signal processing (DSP) systems and for multiprocessor prototyping and task scheduling of software programmable DSP systems using data-flow graph models. See my personal web page for more details.
Selected Publications
- Parhi, Keshab K. "Algorithm Transformation Techniques for Concurrent Processors". Proceedings of the IEEE Special Issue on Supercomputer Technology, 77.12 (December 1989): 1879-1895.
- Parhi, Keshab K., and D. G. Messerschmitt. "Static Rate-Optimal Scheduling of Iterative Data Flow Programs via Optimum Unfolding". IEEE Transactions on Computers, 40.2 (February 1991): 178-195.
- Hatamian, M., and K. K. Parhi. "An 85-MHz Fourth-Order Programmable IIR Digital Filter Chip". IEEE Journal of Solid State Circuits, 27.2 (February 1992): 175-183.