Publications:

    Journal Papers: 

• Hushrav D Mogal, Haifeng Qian, Sachin S Sapatnekar and Kia Bazargan, "Fast and Accurate Statistical Criticality Computation under Process Variations", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), to appear, 2009?
  
• Satish Sivaswamy and Kia Bazargan, "Statistical Analysis and Process Variation-Aware Routing and Skew Assignment for FPGAs", ACM Transactions on Reconfigurable Technology and Systems, Vol 1, No 1, pp. 1-35, Mar 2008
  
• Gang Wang, Satish Sivaswamy, Cristinel Ababei, Kia Bazargan, Ryan Kastner and Eli Bozorgzadeh, "Statistical Analysis and Design of HARP Routing Pattern FPGAs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 2088-2102, Vol. 25, No. 10, October 2006.
  
  
• Cristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, and Sachin S. Sapatnekar, "Placement and Routing in 3D Integrated Circuits", IEEE Design and Test, Vol. 22, No. 6, pp. 520-531, Nov-Dec 2005.
  
  
• Ying Chen, Karthik Ranganathan, Vasudev V Pai, David J. Lilja, and Kia Bazargan, "A Novel Memory Structure for Embedded Systems: Flexible Sequential and Random Access Memory", Journal of Computer Science and Technology (JCST), 2005.
  
  
• Cristinel Ababei, Hushrav Mogal, and Kia Bazargan, "Three-dimensional Place and Route for FPGAs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 25, Issue 6, pp. 1132-1140, June 2006.
  
  
• C. Ababei and K. Bazargan, "Non-Contiguous Linear Placement for Reconfigurable Fabrics",  International Journal of Embedded Systems (IJES) - esp. issue on Reconfigurable Architectures Workshop (RAW), Issue 1/2, Inderscience Publishers, pp. 86-94, 2006.
  
  
• Pongstorn Maidee, Cristinel Ababei, and Kia Bazarga, "Timing-driven Partitioning-based Placement for Island Style FPGAs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 24, No. 3, pp. 395 - 406, Mar. 2005.
  
  
• Jinghuan Chen, Jaekyun Moon, and Kia Bazargan, "FPGA-based Reconfigurable Generation
  of Readback Signals", IEEE Transaction on Magnetics, Vol. 4, No. 3, pp. 1744 - 1750, May 2004..
  
  
• A. Ranjan, K. Bazargan, S. Ogrenci and M. Sarrafzadeh, "Fast Floorplanning for Effective Prediction and Construction",  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 9, Issue 2, pp. 341-351, April 2001.
  
  
• K. Bazargan, R. Kastner and M. Sarrafzadeh,  "3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems", Design Automation for Embedded Systems (DAfES) - RSP'99 Special Issue, April 2000.
  
  
• K. Bazargan, R. Kastner and M. Sarrafzadeh, "Fast Template Placement for Reconfigurable Computing Systems", IEEE Design and Test - Special Issue on Reconfigurable Computing, pp. 68-83, Volume 17 , Issue 1, January, 2000.
  
  
• K. Bazargan, S. Kim and M. Sarrafzadeh, "Nostradamus: A Floorplanner of Uncertain Designs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 18, No. 4, pp. 389-397, April 1999.
  

    Conference papers: 

• Hushrav Mogal, and Kia Bazargan, "Thermal-Aware Floorplanning for Task Migration Enabled Active Sub-threshold Leakage Reduction", International Conference on Computer-Aided Design (ICCAD), 2008.
  
• Pongstorn Maidee, Nagib Hakim and Kia Bazargan, "FPGA Family Composition and Effects of Specialized Blocks", International Conference on Field Programmable Logic and Applications (FPL), 2008.
  
• Hushrav Mogal, Haifeng Qian, Sachin Sapatnekar and Kia Bazargan, "Clustering Based Pruning for Statistical Criticality Computation under Process Variations", International Conference on Computer-Aided Design (ICCAD), 2007.
  
• Pongstorn Maidee and Kia Bazargan, "A Generalized and Unified SPFD-based Rewiring Technique", 17th International Conference on Field Programmable Logic and Applications (FPL), 2007
  
• Satish Sivaswamy and Kia Bazargan, "Statistical Generic And Chip-Specific Skew Assignment for Improving Timing Yield of FPGAs", 17th International Conference on Field Programmable Logic and Applications (FPL), 2007
  
• Satish Sivaswamy and Kia Bazargan, "Variation-AwareRoutingforFPGAs", International Symposium on Field Programmable Gate Arrays (FPGA), 2007.
  
• Hushrav Mogal and Kia Bazargan, "Microarchitecture Floorplanning for Sub-threshold Leakage Reduction", Design and Test in Europe (DATE), 2007.
  
• Pongstorn Maidee and Kia Bazargan, "Defect-tolerant FPGA Architecture Exploration" , 16th International Conference on Field Programmable Logic and Applications (FPL), 2006.
  
  
• Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Eli Bozorgzadeh, "HARP: Hardwired Routing Pattern FPGAs", International Symposium on Field Programmable Gate Arrays (FPGA), pp. 21-29, 2005.
  
  
• C. Ababei, H. Mogal, and K. Bazargan, "3D FPGAs: Placement, Routing and Architecture Evaluation", International Symposium on Field Programmable Gate Arrays (FPGA), (poster), 2005.
  
  
• C. Ababei, H. Mogal, and K. Bazargan, "Three-dimensional Place and Route for FPGAs", Asia South-Pacific Design Automation Conference (ASPDAC), pp. 773 - 778, 2005.
  
  
• C. Ababei, and K. Bazargan, "Exploring Potential Benefits of 3D FPGA Integration", Field-Programmable Logic and its Applications (FPL), 2004.
  
  
• Y. Chen, K. Ranganathan, V. V. Pai, D. Lilja and K. Bazargan, "Enhancing the Memory Performance of Embedded Systems with the Flexible Sequential and Random Access Memory", Asia-Pacific Computer Systems Architecture Conference (ACSAC), 2004.
  
  
• C. Ababei and K. Bazargan, "Non-Contiguous Linear Placement for Reconfigurable Fabrics",  Reconfigurable Architectures Workshop (RAW), p., 2004.
  
  
• W. Choi and K. Bazargan, "Incremental Placement for Timing Optimization",  International Conference on Computer-Aided Design (ICCAD), p., 2003.
  
  
• C. Ababei and K. Bazargan, "Placement Method Targeting Predictability, Robustness and Performance", International Conference on Computer-Aided Design (ICCAD), p., 2003.
  
  
• P. Maidee, C. Ababei and K. Bazargan, "Fast Timing-driven Partitioning-based Placement for Island Style FPGAs", Design Automation Conference (DAC), pp. 598-603, 2003. (slides (zipped ppt))
  
  
• K. Bhasyam and K. Bazargan, "HW/SW Codesign Incorporating Edge Delays Using Dynamic Programming", 
  Euromirco Symposium on Digital Systems Design, p., 2003.
  
  
• V. K. Marreddy, S. Noorbaloochi and and K. Bazargan, "Linear Placement for Static / Dynamic Reconfiguration in JBits", 
  IEEE Symposium on FPGAs for Custom Computing Machines (FCCM), p., 2003.
  
  
• W. Choi and K. Bazargan, "Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration", Design Automation and Test in Europe (DATE), p., 2003.
  
  
• C. Aabei and K. Bazargan, "Timing Minimization by Statistical Timing hMetis-based Partitioning", VLSI Design, pp. 58-63, 2003.
  
  
• C. Aabei, N. Selva, K. Bazargan and G. Karypis, "Multi-objective Circuit Partitioning for Cutsize and Path-Based Delay Minimization", International Conference on Computer-Aided Design (ICCAD), pp. 181-185, 2002.
  
  
• Jinghuan Chen, Jaekyun Moon, and Kia Bazargan, "A Reconfigurable FPGA-Based Readback Signal Generator For Hard-Drive Read Channel Simulator",  Design Automation Conference (DAC), pp. 349-354, 2002.(Slides (zipped ppt))
  
  
• C. Ababei and K. Bazargan,
  "Statistical Timing Driven Partitioning for VLSI Circuits", 
  Design Automation and Test in Europe (DATE), pp. 1109, 2002. (PDF)
  
  
• K. Bazargan, S. Ogrenci and M. Sarrafzadeh,
  "Integrating Scheduling and Physical Design into a Coherent Compilation Cycle for Reconfigurable Computing Architectures",
  Design Automation Conference (DAC), pp. 635-640 , 2001.  (PDF)
  
  
• S. Ogrenci, K. Bazargan and M. Sarrafzadeh,
  "Image analysis and partitioning for FPGA implementation of image restoration", 
  in Proceedings of the IEEE Workshop on Signal Processing Systems pp. 346-355, 2000. 
  
  
• K. Bazargan and M. Sarrafzadeh,
  "Fast Scheduling and Placement Methods for C to Hardware/Software Compilation",
  SPIE International Symposium on Information Technologies, Vol. 4212, November 2000. (PDF) (SLIDES)  
  
  
• A. Ranjan, K. Bazargan and M. Sarrafzadeh,
  "Fast Hierarchical Floorplanning with Congestion and Timing Control",
  IEEE International Conference on Computer Design (ICCD), pp. 357-362, September 2000. (PDF) (SLIDES)  
  
  
• K. Bazargan, R. Kastner, S. Ogrenci and M. Sarrafzadeh,
  "A C to Hardware/Software Compiler",
  IEEE Symposium on FPGAs for Custom Computing Machines (FCCM), pp. 331-332, 2000. (PDF) 
  
  
• K. Bazargan, A. Ranjan and M. Sarrafzadeh,
  "Fast and Accurate Estimation of Floorplans in Logic/High-level Synthesis",
  Great Lakes Symposium on VLSI (GLSV), pp. 95-100, March 2000.
  
  
• R. Kastner, K. Bazargan and M. Sarrafzadeh,
  "Physical Design for Reconfigurable Computing Systems using Firm Templates",
  Workshop on Reconfigurable Computing (WoRC), pp. 19-26, 1999. (PDF) 
  
  
• A. Ranjan, K. Bazargan and M. Sarrafzadeh,
  "Floorplanner 1000 Times Faster: A Good Predictor and Constructor",
  in System-Level Interconnection Prediction (SLIP), pp. 115-120, 1999.(PDF) 
  
  
• K. Bazargan, R. Kastner and M. Sarrafzadeh,
  "3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems",
  10th IEEE International Workshop on Rapid System Prototyping (RSP' 99), pp. 38-43, 1999. (PDF) 
  
  
• K. Bazargan and M. Sarrafzadeh,
  "Fast Online Placement for Reconfigurable Computing Systems",
  IEEE Symposium on FPGAs for Custom Computing Machines (FCCM), pp. 300-302, 1999. (PDF) 
  
  
• K. Bazargan, S. Kim and M. Sarrafzadeh,
  "Nostradamus: A Floorplanner of Uncertain Designs",
  International Symposium on Physical Design (ISPD), pp. 18-23, 1998. (PDF) 

Last update: June 17, 2003