Journal Publications

1987

  1. K.K. Parhi and D.G. Messerschmitt, "Concurrent Cellular VLSI Adaptive Filter Architectures", IEEE Transactionson Circuits and Systems, Vol. CAS-34, No. 10, October 1987, pp. 1141-1151
  2. K.K. Parhi and R.S. Berkowitz, "On Optimizing Importance SamplingSimulations", IEEE Transactions of Circuits and Systems, Vol. CAS-34, No. 12, December 1987, pp. 1558-1563

1989

  1. K.K. Parhi, and D.G. Messerschmitt, "Concurrent Architectures forTwo-Dimensional Recursive Digital Filtering", IEEE Trans. on Circuits and Systems, Vol. CAS-36(6), June 1989, pp. 813-829
  2. K.K. Parhi, and D.G. Messerschmitt, "Pipeline Interleaving and Parallelism in recursive Digital Filters, Part I: Pipelining using Scattered Look-Ahead and Decomposition", IEEE Transactions on Acoustics, Speech, and Signal Processing, Vol. 37(7), July 1989, pp. 1099-1117
  3. K.K. Parhi, and D.G. Messerschmitt, "Pipeline Interleaving and Parallelism in recursive Digital Filters, Part II: Pipelined Incremental Block Filtering",  IEEE Transactions on Acoustics, Speech, and Signal Processing, Vol. 37(7), July 1989, pp. 1118-1135
  4.  K.K. Parhi, "Algorithm Transformation Techniques for Concurrent Processors", Proceedings of the IEEE, Special Issue on Supercomputer Technology, Vol. 77(12), December 1989, pp. 1879-1895

1991

  1. K.K. Parhi, and D.G. Messerschmitt, "Static Rate-Optimal Scheduling of Iterative Data Flow Programs via Optimum Unfolding", IEEE Trans. on Computers, Vol. 40(2), February 1991, pp. 178-195
  2. K.K. Parhi, "A Systematic Approach for Design of Digit-Serial Signal Processing Architectures", IEEE Trans. on Circuits and Systems, Vol. 38, No. 4, April 1991, pp. 358-375
  3. K.K. Parhi, "Pipelining In Dynamic Programming Architectures", IEEE Trans. on Signal Processing, Vol. 39, No. 6, June 1991, pp. 1442-1450
  4. K.K. Parhi, "Finite Word Effects in Pipelined Recursive Filters", IEEE Trans. on Signal Processing, Vol. 39, No. 6, June 1991, pp. 1450-1454
  5. K.K. Parhi, "Pipelining in Algorithms with Quantizer Loops", IEEE Trans. on Circuits and Systems, Vol. 38, No. 7, July 1991, pp. 745-754
  6. K.K. Parhi, "Technology for the 90s: VLSI Signal and Image Processing Systems", IEEE Circuits and Devices Magazine (special technology forecast  issue), 7(4), July 1991 (invited article), pp. 16-17
  7. K.K. Parhi, "Research on VLSI For Digital Video Systems in Japan", Asian Scientific Information Bulletin of the Office of Naval Research Office, 16(4), October - December 1991, pp. 93-98

1992

  1. K.K. Parhi, C.Y. Wang, A.P. Brown, "Synthesis of Control Circuits in Folded Pipelined DSP Architectures", IEEE Journal of Solid State Circuits, Vol. 27, No. 1, January 1992, pp. 29-43
  2. M. Hatamian and K.K. Parhi, "An 85-MHz Fourth-Order Programmable IIR Digital Filter Chip", IEEE Journal of Solid State Circuits, Vol. 27, No. 2, February 1992, pp. 175-183
  3. H.R. Srinivas, and K.K. Parhi, "High-Speed VLSI Arithmetic Processor Architectures Using Hybrid Number Representation", Journal of  VLSI Signal Processing,  Vol. 4, No. 2/3, 1992, pp. 177-198
  4. H.R. Srinivas, and K.K. Parhi, "A Fast VLSI Adder Architecture", IEEE Journal of Solid State Circuits, Vol. 27, No. 5, May 1992, pp. 761-767
  5. K.K. Parhi, "High-Speed VLSI Architectures for Huffman and Viterbi Decoders", IEEE Trans. on Circuits and Systems, Part II: Analog and Digital Signal Processing, Vol. 39, No. 6, June 1992, pp. 385-391
  6. K.K. Parhi, "Video Data Format Converters Using Minimum Number of Registers", IEEE Transactions on Circuits and Systems For Video Technology, Vol. 2, No. 2, June 1992, pp. 255-267
  7. K.K. Parhi, "Systematic Synthesis of DSP Data Format Converters using Life-Time Analysis and Forward-Backward Register Allocation",  IEEE  Trans. on Circuits and Systems, Part II: Analog  and Digital Signal Processing, Vol. 39, No. 7, July 1992, pp. 423-440

1993

  1. N.R. Shanbhag, and K.K. Parhi, "A Pipelined Adaptive Differential Vector Quantizer for Low-Power Speech Coding Applications", IEEE Transactions on Circuits and Systems, Part II: Analog and Digital Signal Processing, 40(5), May 1993, pp. 347-349
  2. N.R. Shanbhag, and K.K. Parhi, "A Pipelined Adaptive Lattice Filter Architecture", IEEE Trans. on Signal Processing, 41(5), May 1993, pp. 1925-1939
  3. K.J. Raghunath, and K.K. Parhi, "Parallel Adaptive Decision Feedback Equalizers", IEEE Transactions on Signal Processing, 41(5), May 1993, pp. 1956-1961
  4. K.K. Parhi, and T. Nishitani, "VLSI Architectures for Discrete Wavelet Transforms", IEEE Trans. on VLSI Systems, 1(2), June 1993, pp. 191-202
  5.  L.E. Lucke, and K.K. Parhi, "Data-Flow Transformations for Critical Path Time Reduction For High-Level DSP Synthesis", IEEE Transactions on Computer Aided Design  of Integrated Circuits And Systems, 12(7), July 1993,  pp. 1063-1068
  6. N.R. Shanbhag, and K.K. Parhi, "Relaxed Look-Ahead Pipelined LMS Adaptive Filters and Their Application to ADPCM Coder", IEEE Transactions on Circuits and Systems, Part II: Analog and Digital Signal Processing, Vol. 40(12), December 1993, pp. 753-766

1994

  1. K.K. Parhi, F.H. Wu, and K. Ganesan, "Sequential and Parallel Neural Network Vector Quantizers", IEEE Transactions on Computers, 43(1), pp. 104-109, January 1994
  2. J.-G. Chung, and K.K. Parhi, "Pipelining of Lattice IIR Digital Filters", IEEE Transactions on Signal Processing, 42(4), pp. 751-761, April 1994
  3. L.E. Lucke, and K.K. Parhi, "Parallel Processing Architectures for Rank-Order and Stack Filters", IEEE Transactions on Signal Processing, 42(5), pp. 1178-1189, May 1994
  4. N.R. Shanbhag, and K.K. Parhi, "Finite Precision Analysis of the ADPCM Coder", IEEE Transactions on Circuits and Systems-Part II: Analog and Digital Signal Processing, 41(5), pp. 364-368, May 1994
  5. K.K. Parhi, "Calculation of Minimum Number of Registers in Arbitrary Life Time Chart", IEEE Circuits and Systems Transactions - Part II: Analog and Digital Signal Processing, 41(6), pp. 434-436, June 1994
  6. N.R. Shanbhag, and K.K. Parhi, "Corrections to "Finite Precision Analysis of the ADPCM Coder"",  IEEE Transactions on Circuits and Systems-Part II: Analog and Digital Signal Processing,  41(7), pp. 493, July 1994
  7. G.B. Adams III, E.J. Coyle, L. Lin, L.E. Lucke, and K.K. Parhi, "Input Compression and Efficient VLSI Architectures for Rank-Order and Stack Filters", Signal Processing,  38, pp. 441-453, August 1994
  8. H.R. Srinivas, B. Vinnakota, and K.K. Parhi, "A C-Testable Carry-Free Divider", IEEE Trans. on VLSI Systems, 2(4), pp. 472-488, December 1994

1995

  1. K.K. Parhi, "High-Level Algorithm and Architecture Transformations for DSP Synthesis",  Journal of VLSI Signal Processing, 9(1), pp. 121-143, January 1995
  2. C.-Y. Wang, and K.K. Parhi, "High-Level DSP Synthesis using Concurrent Transformations, Scheduling, and Allocation", IEEE Transactions on Computer Aided Design, 14(3), pp. 274-295, March 1995
  3. J.-G. Chung, and K.K. Parhi, "Scaled Normalized Lattice Digital Filters", IEEE Transactions on Circuits and Systems - Part II: Analog and Digital Signal Processing, 42(4), pp. 278-282, April 1995
  4. N.R. Shanbhag, and K.K. Parhi, "Pipelined Adaptive DFE Architectures using Relaxed Look-Ahead", IEEE Trans. on Signal Processing, 43(6), pp. 1368-1385, June 1995
  5. H.R. Srinivas, and K.K. Parhi, "A Fast Radix-4 Division Algorithm", IEEE Transactions on Computers, 44(6), pp. 826-831, June 1995
  6. J.-G. Chung, H. Kim and K.K. Parhi, "Pipelined Lattice WDF Design for Wideband Filters", IEEE Trans. on Circuits and Systems, Part II: Analog and Digital Signal Processing, 42(9), pp. 616-618, September 1995
  7. C.-Y. Wang, and K.K. Parhi, "Resource Constrained Loop List Scheduler for DSP Algorithms", Journal of VLSI Signal Processing, 11(1/2), pp. 75-96, October 1995
  8. K. Ito and K.K. Parhi, "Determining the Minimum Iteration Period of an Algorithm", Journal of VLSI Signal Processing, 11(3), pp. 229-244, December 1995

1996

  1. T.C. Denk and K.K. Parhi, "Lower Bounds on Memory Requirements for Statically Scheduled DSP Programs", Journal of VLSI Signal Processing, 12(3), pp. 247-264. June 1996
  2. K.J. Raghunath, and K.K. Parhi, "Pipelined RLS Adaptive Filtering using Scaled Tangent Rotations (STAR)", IEEE Transactions on Signal Processing, 44(10), pp. 2591-2604, October 1996

1997

  1. H.R. Srinivas, K.K. Parhi, and L. Montalvo, "Radix-2 Division with Over-Redundant Quotient Selection", IEEE Trans. on Computers, 46(1), pp. 85-92, Jan. 1997
  2. T.C. Denk and K.K. Parhi, "VLSI Architectures for Lattice Structure Based Orthonormal Discrete Wavelet Transforms", IEEE Transactions on Circuits and Systems, Part - II: Analog and Digital Signal Processing, 44(2), pp. 129-132, Feb. 1997
  3. B. Fu and K.K. Parhi, "Generalized Multiplication Free Arithmetic Codes", IEEE Transactions on Communications, 45(5), pp. 497-501, May 1997
  4. K.J. Raghunath and K.K. Parhi, "Finite Precision Error Analysis of QRD-RLS and STAR-RLS Adaptive Filters", IEEE Transactions on Signal Processing}, 45(5), pp. 1193-1209, May 1997
  5. K. Ito and K.K. Parhi, "A Generalized Technique for Register Counting and its Application to Cost-Optimal DSP Architecture Synthesis", Journal of VLSI Signal Processing, 16(1), pp.  57-72, May 1997
  6. J.H. Satyanarayana and K.K. Parhi, "A Theoretical Approach to Estimation of Bounds on Power Consumption in Digital Multipliers", IEEE Transactions on Circuits and Systems, Part II: Analog and Digital Signal Processing, 44(6), pp. 473-481, June 1997
  7. D.A. Parker and K.K. Parhi, "Low Area/Power Parallel FIR Digital Filter Implementations", Journal of VLSI Signal Processing, 17(1), pp. 75-92, Sept. 1997
  8. Y. Li and K.K. Parhi, "STAR Recursive Least Square Lattice Adaptive Filters", IEEE Trans. on Circuits and Systems, Part II: Analog and Digital Signal Processing, 44(12), pp. 1040-1054, December 1997

1998

  1. S. Jain, L. Song and K.K. Parhi, "Efficient Semi-Systolic VLSI Architectures for Finite Field Arithmetic", IEEE Trans. on VLSI Systems, 6(1), pp. 101-113, March 1998
  2. M. Majumdar and K.K. Parhi, "Synthesis of Low-Area Data Format Converters", IEEE Trans. on Circuits and Systems, Part II: Analog and Digital Signal Processing, 45(4), pp. 504-508, April 1998
  3. L. Song and K.K. Parhi, "Low-Energy Digit-Serial/Parallel Finite Field Multipliers", Journal of VLSI Signal Processing, 19(2), pp. 149-166, June 1998
  4. T.C. Denk and K.K. Parhi, "Exhaustive Scheduling and Retiming of Digital Signal Processing Systems", IEEE Trans. on Circuits and Systems, Part II: Analog and Digital Signal Processing, 45(7), pp. 821-838, July 1998
  5. L. Montalvo, K.K. Parhi, and A. Guyot, "New Svoboda-Tung Division", IEEE Trans. on Computers, 47(9), Sept. 1998
  6. Y.-N. Chang, C.Y. Wang, and K.K. Parhi, "Loop-List Allocation and Scheduling with using Heterogeneous Functional Units", Journal of VLSI Signal Processing, 19(3), pp. 243-256, Aug. 1998
  7. K. Ito, L.E. Lucke and K.K. Parhi, "ILP Based Cost-Optimal DSP Synthesis with Module Selection and Data Format Conversion", IEEE Trans. on VLSI Systems, 6(4), pp. 582-594, Dec. 1998
  8. T.C. Denk and K.K. Parhi, "Synthesis of Folded Pipelined Architectures for Multirate DSP Algorithms", IEEE Trans. on VLSI Systems, 6(4), pp. 595-607, Dec. 1998
  9. Y.-N. Chang, J.H. Satyanarayana and K.K. Parhi, "Systematic Design of High-Speed and Low-Power Digit-Serial Multipliers", IEEE Trans. on Circuits and Systems, Part II: Analog and Digital Signal Processing, 45(12), pp. 1585-1596, Dec. 1998

1999

  1. H.R. Srinivas and K.K. Parhi, "A Floating Point Radix 2 Shared Division/Square-Root Chip", Journal o f VLSI Signal Processing, 21(1), pp. 37-60, May 1999
  2. T.C. Denk and K.K. Parhi, "Two-Dimensional Retiming", IEEE Trans. on VLSI Systems, 7(2), pp. 198-211, June 1999
  3. A.F. Shalash and K.K. Parhi, "Multi-Dimensional Carrierless AM/PM Systems for Digital Subscriber Loops", IEEE Trans. on Communications, 47(11), pp. -, Nov. 1999
  4. K.K. Parhi, "Low-Energy CSMT Carry-Generators and Binary Adders", IEEE Trans. on VLSI Systems, 7(4), pp. -, Dec. 1999

2000

  1. J.H. Satyanarayana and K.K. Parhi, "Theoretical Analysis of Word-Level Switching Activity in the Presence of Glitching and Correlation", IEEE Trans. on VLSI Systems, 8(2), pp. 148-159, Apr. 2000
  2. L. Song, K.K. Parhi, I. Kuroda, T. Nishitani, "Hardware/Software Codesign of Finite Field Datapath for Low-Energy Reed-Solomon Codecs", IEEE Trans. on VLSI Systems, 8(2), pp. 160-172, Apr. 2000
  3. J. Satyanarayana and K.K. Parhi, "Power Estimation of Digital Datapaths using HEAT Tool", IEEE Design and Test Magazine, 17(2), pp. 101-110, April-June 2000
  4. Y.-N. Chang, H. Suzuki and K.K. Parhi, "A 2 Mb/s 256-State 10 mW Rate-1/3 Viterbi Decoder", IEEE Journal of Solid State Circuits, Vol. 35, No. 6, pp. 826-834, June 2000
  5. J.G. Chung, H. Kim and K.K. Parhi, "Angle-Constrained IIR Filter Pipelining for Reduced Roundoff Errors", IEEE Trans. on Circuits and Systems, Part-II: Analog and Digital Signal Processing, 47(6), pp. 555-559, June 2000
  6. Y.-N. Chang and K.K. Parhi, "High-Performance Digit-Serial Complex Multiplier", IEEE Trans. on Circuits and Systems, Part-II: Analog and Digital Signal Processing, 47(6), pp. 570-572, June 2000
  7. A. Shalash and K.K. Parhi, "Power-Efficient Folding of Pipelined LMS Adaptive Filters with Applications to Wireline Digital Communications", Journal of VLSI Signal Processing, 25(3), pp. 199-213, July 2000
  8. J. Ma, K.K. Parhi and E.F. Deprettere, "Annihilation-Reordering Look-Ahead Pipelined CORDIC Based RLS Adaptive Filters and Their Application to Adaptive Beamforming", IEEE Trans. on Signal Processing, 48(8), pp. 2414-2431, Aug. 2000
  9. J. Ma, K.K. Parhi, G.J. Hekstra and E.F. Deprettere, "Efficient Implementations of Pipelined CORDIC Based IIR Digital Filters using Fast Orthonormal Micro-rotations", IEEE Trans. on Signal Processing, 48(9), pp. 2712-2716, Sep. 2000
  10. J. Ma, K.K. Parhi and E.F. Deprettere, "Pipelined CORDIC Based Cascade Orthogonal IIR Digital Filters", IEEE Trans. on Circuits and Systems, Part-II: Analog and Digital Signal Processing, 47(11), pp. 1238-1253, Nov. 2000
  11. L. Gao and K.K. Parhi, "Hierarchical Pipelining and Folding of QRD-RLS Adaptive Filters and Its Application to Digital Beamforming", IEEE Trans. on Circuits and Systems, Part-II: Analog and Digital Signal Processing, 47(12), pp. 1503-1519, Dec. 2000

2001

  1. J. Ma, K.K. Parhi and E.F. Deprettere, "A Unified Algebraic Transformation Approach for Parallel Recursive and Adaptive Filtering and SVD Algorithms", IEEE Trans. on Signal Processing, 49(2), pp. 424-437, Feb. 2001
  2. M. Kuhlmann and K.K. Parhi, "A Novel Low-Power Shared Division and Square-Root using the GST Algorithm", VLSI Design, 12(3), pp. 365-376, 2001
  3. M.E. Zervakis, V. Sundararajan and K.K. Parhi, "Vector Processing of Wavelet Coefficients for Robust Image Denoising", Journal of Image and Vision Computing, Elsevier, 19(7), pp. 435-450, May 2001
  4. T. Zhang and K.K. Parhi, "A Novel Systematic Design Approach for Mastrovito Multipliers over GF(2^m)", IEEE Trans. on Computers, 50(7), pp. 734-749, July 2001
  5. Z. Chi, J. Ma and K.K. Parhi, "Hybrid Annihilation Transformation (HAT) for Pipelining QRD Based Least Square Adaptive Filters", IEEE Trans. on Circuits and Systems, Part-II: Analog and Digital Signal Processing, 48(7), pp. 661-674, July 2001
  6. K.K. Parhi, "Low-Power Implementation of DSP Systems", IEEE Trans. on Circuits and Systems, Part-I: Fundamental Theory and Applications, 48(10), pp. 1214-1224, October 2001
  7. Z. Wang, H. Suzuki and K.K. Parhi, "Finite Wordlength Analysis and Adaptive Decoding for Turbo/MAP Decoders", Journal of VLSI Signal Processing, 29(3), pp. 209-222, November 2001

2002

  1. W.L. Freking and K.K. Parhi, "Performance-Scalable Array Architectures for Modular Multiplication", Journal of VLSI Signal Processing Systems, 31(2), pp. 101-116, April 2002
  2. V. Sundararajan, S. Sapatnekar and K.K. Parhi, "Fast and Exact Transistor Sizing Based on Iterative Relaxation", IEEE Trans. on CAD, 21(5), pp. 568-581, May 2002
  3. M. Kuhlmann and K.K. Parhi, "P-CORDIC: A Precomputation Based CORDIC Algorithm for the Circular Mode", Eurasip Journal on Applied Signal Processing, 2002(9), pp. 436-443, Sept. 2002
  4. J.G. Chung and K.K. Parhi, "Frequency spectrum based low-area low-power parallel FIR filter design", Eurasip Journal on Applied Signal Processing, 2002(9), pp. 444-453, Sept. 2002
  5. J. Valls, M. Kuhlmann, K.K. Parhi, "Evaluation of CORDIC Algorithms for FPGA design", Journal of VLSI Signal Processing, 32(3), pp. 207-222, Nov. 2002
  6. Z. Wang, Z. Chi and K.K. Parhi, "Area-Efficient High Speed Decoding Schemes for Turbo/MAP Decoders", IEEE Trans. on VLSI Systems, 10(12), Dec. 2002
  7. Z. Wang and K.K. Parhi, "On-Line Extraction of Soft Decoding Information and its Applications in VLSI Turbo Codes", IEEE Trans. on Circuits and Systems, Part-II: Analog and Digital Signal Processing ,49(12), pp. 760-769, Dec. 2002
  8. X. Zhang and K.K. Parhi, "Hardware Implementation of Advanced Encryption Standard Algorithm", IEEE CAS Magazine, 2(4), pp. 24-46, Dec. 2002
  9. I. Ben Dhaou, K.K. Parhi and H. Tenhunen, "Energy Efficient Signaling in DSM Technology", VLSI Design: Special Issue on Timing Analysis and Optimization for Deep Sub-Micron ICs, Vol. 15(3), pp. 563-586, 2002

2003

  1. T. Sansaloni, J. Valls and K.K. Parhi, "Digit-Serial Complex Number Multipliers on FPGAs", Journal of VLSI Signal Processing, Vol. 33(1), pp. 101-115, Jan. 2003
  2. Z. Wang and K.K. Parhi, "Performance Improvement and Implementation Issues of Turbo/SOVA Decoders", IEEE Trans. on Communications, Vol. 51(4), pp. 570-579, April 2003
  3. T. Zhang and K.K. Parhi, "An FPGA Implementation of (3,6) Regular Low-Density Parity-Check Code Decoder", Eurasip Journal on Applied Signal Processing, 2003(6), pp. 530-542, May 2003
  4. V. Sundararajan and K.K. Parhi, "Synthesis of Minimum Area Folded Architectures for Multi-Dimensional Multirate DSP Systems", IEEE Trans. on Signal Processing, 51(6), pp. 1954-1965, June 2003
  5. Y.-N. Chang and K.K. Parhi, "An Efficient Pipelined FFT Implementation", IEEE Trans. on Circuits and Systems: Part-II: Analog and Digital Signal Processing, Vol. 50(6), pp. 322-325, June 2003
  6. V. Sundararajan, S. S. Sapatnekar, and K. K. Parhi, "A New Approach for Integration of Min-Area Retiming and Min-Delay Padding for Simultaneously Addressing Short-path and Long-path Constraints," ACM Transactions on Design Automation of Electronic Systems, Vol. 9, No. 3, pp. 273 - 289, July 2004.
  7. B. Sahoo and K.K. Parhi, "A Low Power Correlator for CDMA Wireless Systems", Journal of VLSI Signal Processing, 35(1), pp. 105-112, August 2003
  8. L. Gao, K.K. Parhi and J. Ma, "Relaxed Annihilation-Reordering Look-Ahead QRD-RLS Adaptive Filters", Journal of VLSI Signal Processing, Vol. 35(2), pp. 119-136, Sept. 2003
  9. J. Kong and K.K. Parhi, "Interleaved Convolutional Code and its Viterbi Decoder Architecture", EURASIP Journal on Applied Signal Processing, Vol. 2003(13), pp. 1328-1324, 2003
  10. Y. Chen and K.K. Parhi, "Reduced Complexity Decoding Algorithms for Space-Time Block Turbo Coded System", EURASIP Journal on Applied Signal Processing, Vol. 2003(13), pp. 1335-1345, 2003
  11. S.-M. Kim, J.-G. Chung and K. K. Parhi, "Low error CSD Fixed-Width Multiplier with Efficient Sign Extension", IEEE Trans. on Circuits and Systems, Part-II: Analog and Digital Signal Processing, 50(3), pp. 984-993, December 2003

2004

  1. Z. Chi, L. Song and K.K. Parhi, "On the Performance, Complexity Tradeoffs of Block Turbo Decoder Design", IEEE Communications Letters, Vol. 52, No. 2, pp. 173-175, Feb. 2004
  2. K.K. Parhi, "An Improved Pipelined MSB-First Add-Compare-Select Unit Structure for Viterbi Decoders", IEEE Trans. on Circuits and Systems, Part-I: Regular Papers, 51(3), pp. 504-511, March 2004
  3. K. K. Parhi, "Eliminating the Fanout Bottleneck in Parallel Long BCH Encoders", IEEE Trans. on Circuits and Systems, Part-I: Regular Papers, 51(3), pp. 512-516, March 2004
  4. T. Zhang and K.K. Parhi, "Joint (3,k)-regular LDPC Code and Decoder/Encoder Design", IEEE Trans. Signal Processing, 52(4), pp. 1065-1079, April 2004
  5. K.-J. Cho, K.-C. Lee, J.-G. Chung, and K.K. Parhi, "Design of Low-Error Fixed Width Modified Booth Multiplier", IEEE Trans. on VLSI Systems, 12(5), pp. 522-531, May 2004
  6. J. Kong and K.K. Parhi, "Low-Latency Architectures for High-Throughput Viterbi Decoders", IEEE Trans. on VLSI Systems, 12(6), pp. 642-651, June 2004
  7. Y. Chen and K.K. Parhi, "Small Area Parallel Chien search Architectures for Long BCH Codes", IEEE Trans. on VLSI Systems, 12(5), pp. 545-549, May 2004
  8. Y. Chen and K.K. Parhi, "Overlapped Message Passing of Quasi-Cyclic Low-Density Parity Check Codes", IEEE Trans. on Circuits and Systems, Part-I: Regular Papers, 51(6), pp. 1106-1113, June 2004
  9. J. Ma and K.K. Parhi, "Pipelined CORDIC Based State-Space Orthogonal Recursive Digital Filters using Matrix Look-Ahead", IEEE Trans. Signal Processing, 52(7), pp. 2102-2119, July 2004
  10. V. Sundararajan, S. Sapatnekar and K.K. Parhi, "A New Approach for Integration of Min-Area Retiming and Min-Delay Padding for Simultaneously Addressing Short Path and Long Path constraints. ACM Trans. on TODAES, 9(3), pp. 273-289, July 2004
  11. C. Cheng and K.K. Parhi, "Hardware Efficient Fast Parallel FIR Filter Structures Based on Iterated Short Convolution", IEEE Trans. on Circuits and Systems, Part-I: Regular Papers, 51(8), pp. 1492-1500, Aug. 2004
  12. X. Zhang and K.K. Parhi, "High-Speed VLSI Architectures for the AES Algorithm", IEEE Trans. on VLSI Systems, 12(9), pp. 957-967, Sep. 2004
  13. Y. Chen and K.K. Parhi, "On the Performance and Implementation Issues of Interleaved Single Parity Check Turbo Product Codes" Journal of VLSI Signal Processing Systems, 35(1), Jan. 2005
  14. Z. Chi, Z. Wang and K.K. Parhi, "On the Better Protection of Short Frame Turbo Codes", IEEE Trans. on Communications, 52(9), pp. 1435-1439, Sept. 2004

2005

  1. Y. Chen and K.K. Parhi, "On the Performance and Implementation Issues of Interleaved Single Parity Check Turbo Product Codes" Journal of VLSI Signal Processing Systems, 35(1), Jan. 2005
  2. X. Zhang and K.K. Parhi, "Fast Factorization Architecture in Soft-Decision Reed-Solomon Decoding", IEEE Trans. on VLSI Systems, 13(4), pp. 413-426, Apr. 2005
  3. K.K. Parhi, "Design of Multi-Gigabit Multiplexer Loop Based Decision Feedback Equalizers", IEEE Trans. on VLSI Systems, 13(4), pp. 489-493, Apr. 2005
  4. C. Cheng and K.K. Parhi, "A Novel Systolic Array Structure for DCT", IEEE Trans. on Circuits and Systems, Part-II: Express Briefs, 52(5), pp. 366-369, July 2005
  5. X. Zhang and K.K. Parhi, "High-Speed Architectures for Parallel Long BCH Encoders", IEEE Trans. on VLSI Systems, 13(7), pp. 872-877, July 2005

2006

  1. C. Cheng and K.K. Parhi, "Hardware Efficient Fast Computation of the Discrete Fourier Transform", Springer Journal of VLSI Signal Processing, pp. 159-172, 42(2), Feb. 2006
  2. Y. Gu and K.K. Parhi, "Interleaved Trellis Coded Modulation and Decoder Optimizations for 10 Gigabit Ethernet over Copper", Journal of VLSI Signal Processing Systems, 44(3), pp. 211-221, March 2006
  3. L. Gao and K.K. Parhi, "Models for Architectural Power and Power Grid Noise Analysis on Data Bus", Journal of VLSI Signal Processing Systems, 44(2), pp. 25-46, August 2006
  4. J.-H. Lin and K.K. Parhi, "Parallelization of Context Based Adaptive Binary Arithmetic Coders", IEEE Trans. on Signal Processing, 54(10), pp. 3702-3711, Oct. 2006
  5. C. Cheng and K.K. Parhi, "High-Speed Parallel CRC Implementation Based on Unfolding, Pipelining and Retiming", IEEE Trans. Circuits and Systems-II: Express Briefs, 53(10), pp. 1017-1021, Oct. 2006
  6. X. Zhang and K.K. Parhi, "On the Optimum Constructions of Composite Field for the AES Algorithm", IEEE Trans. Circuits and Systems-II: Express Briefs, 53(10), pp. 1153-1157, Oct. 2006
  7. C. Cheng and K.K. Parhi, "Hardware Efficient Fast DCT Based on Novel Cyclic Convolution Structures", IEEE Trans. on Signal Processing, 54(11), pp. 4419-4434, Nov. 2006

2007

  1. K.-J. Cho, J.-S. Park, B.-K. Kim, J.-G. Chung and K.K. Parhi, "Design of a Sample-Rate Converter From CD to DAT Using Fractional Delay Allpass Filter", IEEE Trans. on Circuits and Systems, Part-II: Express Briefs, 54(1), pp. 19-23, Jan. 2007
  2. Y. Gu and K.K. Parhi, "Pipelined Parallel Decision Feedback Decoders (PDFDs) for High-Speed Ethernet over Copper", IEEE Trans. on Signal Processing, 55(2), pp. 707-715, Feb. 2007
  3. C. Cheng and K.K. Parhi, "Low Cost Parallel FIR Filter Structures with 2-Stage Parallelism", IEEE Trans. Circuits and Systems-I: Regular Papers, 54(2), pp. 280-290, Feb. 2007
  4. C. Cheng and K.K. Parhi, "Low-Cost Fast VLSI Algorithm for Discrete Fourier Transform", IEEE Trans. Circuits and Systems-I: Regular Papers, 54(4), pp. 791-806, Apr. 2007
  5. Y. Gu and K.K. Parhi, "High-Speed Architecture Design of Tomlinson-Harashima Precoders", IEEE Trans. Circuits and Systems-I: Regular Papers, 54(9), pp. 1929-1937, Sep. 2007
  6. C. Cheng and K.K. Parhi, "High-Throughput VLSI Architecture for FFT Computation", IEEE Trans. Circuits and Systems-II: Express Briefs, 54(10), pp. 864-867, Oct. 2007

2008

  1. C. Cheng and K.K. Parhi, "High-Speed VLSI Implementation of 2-D Discrete Wavelet Transform", IEEE Trans. on Signal Processing, 56(1), pp. 393-403, Jan. 2008
  2. Y. Gu and K.K. Parhi, "Design of Parallel Tomlinson-Harashima Precoders", IEEE Trans. Circuits and Systems-II: Express Briefs, 55(5), pp. 447-451, May 2008
  3. J. Chen, Y. Gu and K.K. Parhi, "Low Complexity ECHO And NEXT Cancellers for High-Speed Ethernet Transceivers", IEEE Trans. Circuits and Systems-I: Regular Papers, 55(9), pp. 2827-2840, Oct. 2008
  4. C. Cheng and K.K. parhi, "Hardware-Efficient Low-Latency Architecture for High-Throughput Rate Viterbi Decoders", IEEE Trans. Circuits and Systems-II: Express Briefs, 55(12), pp. 1254-1258, Dec. 2008

2009 and In Press...

  1. E. Saberinia, J. Tang, A.H. Tewfik, and K.K. Parhi, "Pulsed OFDM Modulation for Ultra Wideband Communications", IEEE Trans. on Vehicular Technology , 58(2), pp. 720-726, Feb. 2009
  2. S. Park, K.K. Parhi, and S.-C. Park, "Probabilistic Spherical Detection and VLSI Implementation for Multiple Antenna Systems", IEEE Trans. Circuits and Systems-I: Regular Papers, 56(3), pp. 685-698, March 2009
  3. J. Chen, Y. Gu and K.K. Parhi, "Novel FEXT Cancellation and Equalization for High-Speed Ethernet Transceivers", IEEE Trans. Circuits and Systems-I: Regular Papers, 56(6), pp. 1272-1285, June 2009
  4. R. Liu and K.K. Parhi, "Low-Latency Low-Complexity Architectures for Viterbi Decoders", IEEE Trans. Circuits and Systems-I: Regular Papers, to appear
  5. M. Garrido, K.K. Parhi, and J. Grajal, "A Pipelined FFT Architecture for Real-Valued Signals", IEEE Trans. Circuits and Systems-I: Regular Papers, to appear
  6. A.E. Cohen and K.K. Parhi, "A Low-Complexity Hybrid LDPC Code Encoder for IEEE 802.3an (10GBase-T) Ethernet", IEEE Trans. Signal Processing, to appear
  7. D. Oh and K.K. Parhi "Low-Complexity Decoder Architecture for Low-density Parity Check Codes", Journal of VLSI Signal Processing Systems , to appear
  8. D. Oh and K.K. Parhi "Minsum Decoder Architecture with Reduced Word-Length for LDPC Codes", IEEE Trans. Circuits and Systems-I: Regular Papers, to appear
  9. D. Oh and K.K. Parhi, "Low-Complexity Switch Networks for Reconfigurable LDPC Decoders", IEEE Trans. VLSI Systems , to appear
  10. Y. Liu, T. Zhang and K.K. Parhi, "Computation Error Analysis in Digital Signal Processing System with Overscaled Supply Voltage", IEEE Trans. VLSI Systems , to appear
  11. A.E. Cohen and K.K. Parhi, "Fast Elliptic Curve Cryptography Acceleration for GF(2^m) on 32-Bit Processors", Journal of VLSI Signal Processing Systems , to appear
 

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