2004

Z. Chi, L. Song and K.K. Parhi,
"A study on the Performance,
Complexity Tradeoffs of Block Turbo Decoder Design",
IEEE Communications Letters, Vol. 52, No. 2,
pp. 173175, Feb. 2004

K.K. Parhi,
"An Improved Pipelined MSBFirst AddCompareSelect
Unit Structure for Viterbi Decoders",
IEEE Trans. on Circuits and Systems,
PartI: Regular Papers, 51(3), pp. 504511, March 2004

K. K. Parhi,
"Eliminating the Fanout Bottleneck in Parallel
Long BCH Encoders",
IEEE Trans. on Circuits and Systems,
PartI: Regular Papers, 51(3), pp. 512516, March 2004

T. Zhang and K.K. Parhi,
"Joint (3,k)regular
LDPC Code and Decoder/Encoder Design",
IEEE Trans. Signal Processing, 52(4), pp. 10651079,
April 2004

K.J. Cho, K.C. Lee, J.G. Chung, and K.K. Parhi,
"Design of LowError Fixed Width Modified Booth Multiplier",
IEEE Trans. on VLSI Systems, 12(5), pp. 522531, May 2004

J. Kong and K.K. Parhi,
"LowLatency Architectures for
HighThroughput Viterbi Decoders",
IEEE Trans. on VLSI Systems, 12(6), pp. 642651, June 2004

Y. Chen and K.K. Parhi,
"Small Area Parallel Chien search
Architectures for Long BCH Codes",
IEEE Trans. on VLSI Systems, 12(5), pp. 545549, May 2004

Y. Chen and K.K. Parhi,
"Overlapped Message Passing of
QuasiCyclic LowDensity Parity Check Codes",
IEEE Trans. on Circuits and Systems,
PartI: Regular Papers, 51(6), pp. 11061113, June 2004

J. Ma and K.K. Parhi,
"Pipelined CORDIC Based
StateSpace Orthogonal Recursive Digital Filters using
Matrix LookAhead",
IEEE Trans. Signal Processing, 52(7), pp. 21022119, July 2004

V. Sundararajan, S. Sapatnekar and K.K. Parhi,
"A New Approach for Integration of MinArea Retiming
and MinDelay Padding for Simultaneously Addressing
Short Path and Long Path constraints",
ACM Trans. on TODAES, 9(3), pp. 273289, July 2004

C. Cheng and K.K. Parhi,
"Hardware Efficient Fast Parallel FIR Filter Structures Based
on Iterated Short Convolution",
IEEE Trans. on Circuits and Systems,
PartI: Regular Papers, 51(8), pp. 14921500, Aug. 2004

X. Zhang and K.K. Parhi,
"HighSpeed VLSI
Architectures for the AES Algorithm",
IEEE Trans. on VLSI Systems, 12(9), pp. 957967, Sep. 2004

Z. Chi, Z. Wang and K.K. Parhi,
"On the Better Protection of Short Frame Turbo Codes",
IEEE Trans. on Communications, 52(9), pp. 14351439, Sept. 2004
2003

T. Sansaloni, J. Valls and K.K. Parhi,
"DigitSerial Complex Number Multipliers on FPGAs",
Journal of VLSI Signal Processing, Vol. 33(12), pp. 105115, Jan. 2003

Z. Wang and K.K. Parhi,
"Performance Improvement and Implementation
Issues of Turbo/SOVA Decoders",
IEEE Trans. on Communications, Vol. 51(4), pp. 570579, April 2003

T. Zhang and K.K. Parhi, <
"An FPGA Implementation of
(3,6) Regular LowDensity ParityCheck Code Decoder",
Eurasip Journal on Applied
Signal Processing, 2003(6), pp. 530542, May 2003

V. Sundararajan and K.K. Parhi,
"Synthesis of
Minimum Area Folded Architectures for Rectangular MultiDimensional
Multirate DSP Systems",
IEEE Trans. on Signal Processing, 51(7),
pp. 19541965, July 2003

Y.N. Chang and K.K. Parhi,
"An Efficient Pipelined
FFT Implementation",
IEEE Trans. on Circuits and Systems: PartII:
Analog and Digital Signal Processing,
Vol. 50(6), pp. 322325, June 2003

V. Sundararajan, S. S. Sapatnekar, and K. K. Parhi,
"A New Approach for Integration of MinArea Retiming
and MinDelay Padding for Simultaneously Addressing
Shortpath and Longpath Constraints,"
ACM Transactions on Design Automation of Electronic Systems, Vol. 9,
No. 3, pp. 273  289, July 2004.

B. Sahoo and K.K. Parhi,
"A Low Power
Correlator for CDMA Wireless Systems",
Journal of VLSI Signal Processing, 35(1),
pp. 105112, August 2003

L. Gao, K.K. Parhi and J. Ma,
"Relaxed AnnihilationReordering LookAhead
QRDRLS Adaptive Filters",
Journal of VLSI Signal
Processing, Vol. 35(2), pp. 119135, Sept. 2003

J. Kong and K.K. Parhi,
"Interleaved Convolutional Code
and its Viterbi Decoder Architecture",
EURASIP Journal on Applied Signal Processing,
Vol. 2003(13), pp. 13281334, 2003

Y. Chen and K.K. Parhi,
"Low Complexity Decoding Algorithms of
Block Turbo Coded System" with Antenna Diversity,
EURASIP Journal on Applied Signal Processing,
Vol. 2003(13), pp. 13351345, 2003

S.M. Kim, J.G. Chung and K. K. Parhi,
"Low error CSD FixedWidth
Multiplier with Efficient Sign Extension",
IEEE Trans. on Circuits and Systems,
PartII: Analog and Digital Signal Processing, 50(3),
pp. 984993, December 2003
2002

W.L. Freking and K.K. Parhi,
"PerformanceScalable Array Architectures for Modular Multiplication",
Journal of VLSI Signal Processing Systems,
31(2), pp. 101116, April 2002

V. Sundararajan, S. Sapatnekar and K.K. Parhi,
"Fast and Exact Transistor Sizing Based on
Iterative Relaxation",
IEEE Trans. on CAD, 21(5), pp. 568581, May 2002

M. Kuhlmann and K.K. Parhi,
"PCORDIC: A Precomputation
Based CORDIC Algorithm for the Circular Mode",
Eurasip Journal on Applied Signal Processing,
2002(9), pp. 936943, Sept. 2002

J.G. Chung and K.K. Parhi,
"Frequency spectrum based lowarea lowpower parallel FIR filter design",
Eurasip Journal on Applied Signal Processing,
2002(9), pp. 944953, Sept. 2002

J. Valls, M. Kuhlmann, K.K. Parhi,
"Evaluation of CORDIC Algorithms for
FPGA design",
Journal of VLSI Signal Processing,
32(3), pp. 207222, Nov. 2002

Z. Wang, Z. Chi and K.K. Parhi,
"AreaEfficient
High Speed Decoding Schemes for Turbo/MAP Decoders",
IEEE Trans. on VLSI Systems, 10(12), pp. 902912, Dec. 2002

Z. Wang and K.K. Parhi,
"OnLine Extraction of
Soft Decoding Information and its Applications in VLSI
Turbo Codes", IEEE Trans. on Circuits and Systems,
PartII: Analog and Digital Signal Processing ,49(12), pp. 760769, Dec. 2002

X. Zhang and K.K. Parhi,
"Hardware Implementation of
Advanced Encryption Standard Algorithm",
IEEE CAS Magazine, 2(4), pp. 2446, Dec. 2002

I. Ben Dhaou, K.K. Parhi and H. Tenhunen,
"Energy Efficient Signaling in Deepsubmicron Technology",
VLSI Design: Special Issue on Timing
Analysis and Optimization for Deep SubMicron ICs,
Vol. 15(3), pp. 563586, 2002
2001

J. Ma, K.K. Parhi and E.F. Deprettere,
"A Unified Algebraic Transformation Approach for Parallel Recursive and Adaptive
Filtering and SVD Algorithms",
IEEE Trans. on Signal Processing,
49(2), pp. 424437, Feb. 2001

M. Kuhlmann and K.K. Parhi,
"A Novel LowPower Shared Division and
SquareRoot using the GST Algorithm",
VLSI Design, 12(3), pp. 365376, 2001

M.E. Zervakis, V. Sundararajan and K.K. Parhi,
"Vector Processing of Wavelet Coefficients for Robust Image Denoising",
Journal of Image and Vision Computing, Elsevier,
19(7), pp. 435450, May 2001

T. Zhang and K.K. Parhi,
"A Novel Systematic Design Approach for Mastrovito Multipliers
over GF(2^m)",
IEEE Trans. on Computers,
50(7), pp. 734749, July 2001

Z. Chi, J. Ma and K.K. Parhi,
"Hybrid Annihilation Transformation (HAT) for Pipelining QRD Based
Least Square Adaptive Filters",
IEEE Trans. on Circuits and Systems, PartII: Analog
and Digital Signal Processing, 48(7), pp. 661674, July 2001

K.K. Parhi,
"LowPower Implementation of DSP Systems",
IEEE Trans. on Circuits and Systems,
PartI: Fundamental Theory and Applications,
48(10), pp. 12141224, October 2001

Z. Wang, H. Suzuki and K.K. Parhi,
"Finite Wordlength Analysis and Adaptive Decoding for
Turbo/MAP Decoders",
Journal of VLSI Signal Processing,
29(3), pp. 209222, November 2001
2000

J.H. Satyanarayana and K.K. Parhi,
"Theoretical Analysis of WordLevel Switching Activity in the Presence of Glitching and Correlation",
IEEE Trans. on VLSI Systems, 8(2), pp. 148159, Apr. 2000

L. Song, K.K. Parhi, I. Kuroda, T. Nishitani,
"Hardware/Software Codesign of Finite Field Datapath for
LowEnergy ReedSolomon Codecs",
IEEE Trans. on VLSI Systems, 8(2), pp. 160172, Apr. 2000

J. Satyanarayana and K.K. Parhi,
"Power Estimation of Digital Datapaths using HEAT Tool",
IEEE Design and Test Magazine, 17(2), pp. 101110, AprilJune 2000

Y.N. Chang, H. Suzuki and K.K. Parhi,
"A 2 Mb/s 256State
10 mW Rate1/3 Viterbi Decoder,"
IEEE Journal of Solid State Circuits,
Vol. 35, No. 6, pp. 826834, June 2000

J.G. Chung, H. Kim and K.K. Parhi,
"AngleConstrained IIR Filter Pipelining for Reduced Roundoff Errors",
IEEE Trans. on Circuits and Systems, PartII: Analog
and Digital Signal Processing, 47(6), pp. 555559, June 2000

Y.N. Chang and K.K. Parhi,
"HighPerformance DigitSerial Complex Multiplier",
IEEE Trans. on Circuits and Systems, PartII: Analog
and Digital Signal Processing, 47(6), pp. 570572, June 2000

A. Shalash and K.K. Parhi,
"PowerEfficient Folding of Pipelined LMS Adaptive Filters with
Applications to Wireline Digital Communications",
Journal of VLSI Signal Processing, 25(3), pp. 199213, July 2000

J. Ma, K.K. Parhi and E.F. Deprettere,
"AnnihilationReordering LookAhead Pipelined CORDIC Based RLS Adaptive Filters and Their
Application to Adaptive Beamforming",
IEEE Trans. on Signal Processing, 48(8), pp. 24142431, Aug. 2000

J. Ma, K.K. Parhi, G.J. Hekstra and E.F. Deprettere,
"Efficient Implementations of Pipelined CORDIC
Based IIR Digital Filters using Fast Orthonormal
Microrotations",
IEEE Trans. on Signal Processing, 48(9), pp. 27122716, Sep. 2000

J. Ma, K.K. Parhi and E.F. Deprettere,
"Pipelined CORDIC Based Cascade Orthogonal IIR Digital Filters",
IEEE Trans. on Circuits and Systems, PartII: Analog
and Digital Signal Processing, 47(11), pp. 12381253, Nov. 2000

L. Gao and K.K. Parhi,
"Hierarchical Pipelining
and Folding of QRDRLS Adaptive Filters and Its Application to
Digital Beamforming,"
IEEE Trans. on Circuits and Systems, PartII: Analog
and Digital Signal Processing, 47(12), pp. 15031519, Dec. 2000
1999

H.R. Srinivas and K.K.
Parhi,
"A Floating Point Radix 2 Shared Division/SquareRoot Chip," Journal of
VLSI Signal Processing,
21(1), pp. 3760, May 1999

T.C. Denk and
K.K. Parhi,
"TwoDimensional Retiming [VLSI Design]," IEEE Trans. on VLSI Systems,
7(2), pp. 198211, June 1999

A.F. Shalash and K.K. Parhi,
"MultiDimensional Carrierless AM/PM Systems for Digital Subscriber Loops,"
IEEE Trans. on Communications,
47(11), pp. 16551667, Nov. 1999

K.K. Parhi,
"LowEnergy CSMT CarryGenerators and Binary Adders," IEEE Trans. on VLSI Systems,
7(4), pp. 450462, Dec. 1999
1998

S. Jain, L. Song
and K.K. Parhi,
"Efficient SemiSystolic VLSI Architectures for Finite
Field Arithmetic," IEEE Trans. on VLSI Systems, 6(1), pp.
101113, March 1998

M. Majumdar and
K.K. Parhi,
"Design of Data Format Converters using TwoDimensional Register Allocation," IEEE Trans.
on Circuits and Systems, Part II: Analog and Digital Signal Processing,
45(4), pp. 504508, April 1998

L. Song and K.K.
Parhi,
"LowEnergy DigitSerial/Parallel Finite Field Multipliers", Journal
of VLSI Signal Processing, 19(2), pp. 149166, June 1998

T.C. Denk and
K.K. Parhi,
"Exhaustive Scheduling and Retiming of Digital Signal Processing
Systems," IEEE Trans. on Circuits and Systems, Part II: Analog and Digital
Signal Processing, 45(7), pp. 821838, July 1998

L. Montalvo, K.K.
Parhi, and A. Guyot,
"New SvobodaTung Division," IEEE Trans. on Computers,
47(9), pp. 10141020, Sept. 1998

Y.N. Chang, C.Y.
Wang, and K.K. Parhi,
"LoopList Allocation and Scheduling with using Heterogeneous
Functional Units," Journal of VLSI Signal Processing, 19(3), pp. 243256, Aug. 1998

K. Ito, L.E. Lucke
and K.K. Parhi,
"ILP Based CostOptimal DSP Synthesis with Module Selection
and Data Format Conversion," IEEE Trans. on VLSI Systems, 6(4), pp. 582594, Dec. 1998

T.C. Denk and
K.K. Parhi,
"Synthesis of Folded Pipelined Architectures for Multirate
DSP Algorithms," IEEE Trans. on VLSI Systems, 6(4), pp. 595607, Dec. 1998

Y.N. Chang,
J.H.
Satyanarayana and K.K. Parhi,
"Systematic Design of HighSpeed and
LowPower
DigitSerial Multipliers," IEEE Trans. on Circuits and
Systems, Part II: Analog and Digital Signal Processing,
45(12), pp. 15851596, Dec. 1998
1997

H.R. Srinivas,
K.K. Parhi, and L. Montalvo,
"Radix2 Division with OverRedundant Quotient
Selection," IEEE Trans. on Computers, 46(1), pp. 8592, Jan.
1997

T.C. Denk and
K.K. Parhi,
"VLSI Architectures for Lattice Structure Based Orthonormal
Discrete Wavelet Transforms," IEEE Transactions on Circuits and Systems,
Part  II: Analog and Digital Signal Processing, 44(2), pp.
129132, Feb. 1997

B. Fu and K.K.
Parhi,
"Generalized Multiplication Free Arithmetic Codes," IEEE Transactions
on Communications, 45(5), pp. 497501, May 1997

K.J. Raghunath
and K.K. Parhi,
"Finite Precision Error Analysis of QRDRLS and STARRLS
Adaptive Filters," IEEE Transactions on Signal Processing}, 45(5),
pp. 11931209, May 1997

K. Ito and K.K.
Parhi,
"A Generalized Technique for Register Counting and its Application
to CostOptimal DSP Architecture Synthesis," Journal of VLSI Signal
Processing, 16(1), pp. 5772, May 1997

J.H. Satyanarayana
and K.K. Parhi,
"A Theoretical Approach to Estimation of Bounds on Power
Consumption in Digital Multipliers," IEEE Transactions on Circuits and
Systems, Part II: Analog and Digital Signal Processing, 44(6),
pp. 473481, June 1997

D.A. Parker and
K.K. Parhi,
"Low Area/Power Parallel FIR Digital Filter Implementations,"
Journal of VLSI Signal Processing, 17(1), pp. 7592, Sept.
1997

Y. Li and K.K.
Parhi,
"STAR Recursive Least Square Lattice Adaptive Filters," IEEE
Trans. on Circuits and Systems, Part II: Analog and Digital Signal Processing,
44(12), pp. 10401054, December 1997
1996

T.C. Denk and
K.K. Parhi,
"Lower Bounds on Memory Requirements for Statically Scheduled
DSP Programs," Journal of VLSI Signal Processing, 12(3),
pp. 247264. June 1996

K.J. Raghunath,
and K.K. Parhi,
"Pipelined RLS Adaptive Filtering using Scaled Tangent
Rotations (STAR)," IEEE Transactions on Signal Processing, 44(10),
pp. 25912604, October 1996
1995

K.K. Parhi,
"HighLevel
Algorithm and Architecture Transformations for DSP Synthesis," Journal
of VLSI Signal Processing, 9(1), pp. 121143, January 1995

C.Y. Wang, and
K.K. Parhi,
"HighLevel DSP Synthesis using Concurrent Transformations,
Scheduling, and Allocation," IEEE Transactions on Computer Aided Design,
14(3), pp. 274295, March 1995

J.G. Chung, and
K.K. Parhi,
"Scaled Normalized Lattice Digital Filters," IEEE Transactions
on Circuits and Systems  Part II: Analog and Digital Signal Processing,
42(4), pp. 278282, April 1995

N.R. Shanbhag,
and K.K. Parhi,
"Pipelined Adaptive DFE Architectures using Relaxed LookAhead,"
IEEE Trans. on Signal Processing, 43(6), pp. 13681385, June
1995

H.R. Srinivas,
and K.K. Parhi,
"A Fast Radix4 Division Algorithm," IEEE Transactions
on Computers, 44(6), pp. 826831, June 1995

J.G. Chung, H.
Kim and K.K. Parhi,
"Pipelined Lattice WDF Design for Wideband Filters,"
IEEE Trans. on Circuits and Systems, Part II: Analog and Digital
Signal Processing, 42(9), pp. 616618, September 1995

C.Y. Wang, and
K.K. Parhi,
"Resource Constrained Loop List Scheduler for DSP Algorithms,"
Journal of VLSI Signal Processing, 11(1/2), pp. 7596, October
1995

K. Ito and K.K.
Parhi,
"Determining the Minimum Iteration Period of an Algorithm," Journal
of VLSI Signal Processing, 11(3), pp. 229244, December 1995
1994

K.K. Parhi, F.H.
Wu, and K. Ganesan,
"Sequential and Parallel Neural Network Vector Quantizers,"
IEEE Transactions on Computers, 43(1), pp. 104109, January
1994

J.G. Chung, and
K.K. Parhi,
"Pipelining of Lattice IIR Digital Filters," IEEE Transactions
on Signal Processing, 42(4), pp. 751761, April 1994

L.E. Lucke, and
K.K. Parhi,
"Parallel Processing Architectures for RankOrder and Stack
Filters," IEEE Transactions on Signal Processing, 42(5),
pp. 11781189, May 1994

N.R. Shanbhag,
and K.K. Parhi,
"Finite Precision Analysis of the ADPCM Coder," IEEE
Transactions on Circuits and SystemsPart II: Analog and Digital Signal
Processing, 41(5), pp. 364368, May 1994

K.K. Parhi,
"Calculation
of Minimum Number of Registers in Arbitrary Life Time Chart," IEEE Circuits
and Systems Transactions  Part II: Analog and Digital Signal Processing,
41(6), pp. 434436, June 1994

N.R. Shanbhag,
and K.K. Parhi,
"Corrections to "Finite Precision Analysis of the ADPCM
Coder," IEEE Transactions on Circuits and SystemsPart II: Analog
and Digital Signal Processing, 41(7), pp. 493, July 1994

G.B. Adams III,
E.J. Coyle, L. Lin, L.E. Lucke, and K.K. Parhi,
"Input Compression and
Efficient VLSI Architectures for RankOrder and Stack Filters," Signal
Processing, 38, pp. 441453, August 1994

H.R. Srinivas,
B. Vinnakota, and K.K. Parhi,
"A CTestable CarryFree Divider," IEEE
Trans. on VLSI Systems, 2(4), pp. 472488, December 1994
1993

N.R. Shanbhag,
and K.K. Parhi,
"A Pipelined Adaptive Differential Vector Quantizer for
LowPower Speech Coding Applications," IEEE Transactions on Circuits
and Systems, Part II: Analog and Digital Signal Processing, 40(5),
May 1993, pp. 347349

N.R. Shanbhag,
and K.K. Parhi,
"A Pipelined Adaptive Lattice Filter Architecture," IEEE
Trans. on Signal Processing, 41(5), May 1993, pp. 19251939

K.J. Raghunath,
and K.K. Parhi,
"Parallel Adaptive Decision Feedback Equalizers," IEEE
Transactions on Signal Processing, 41(5), May 1993, pp. 19561961

K.K. Parhi, and
T. Nishitani,
"VLSI Architectures for Discrete Wavelet Transforms," IEEE
Trans. on VLSI Systems, 1(2), June 1993, pp. 191202

L.E. Lucke,
and K.K. Parhi,
"DataFlow Transformations for Critical Path Time Reduction
For HighLevel DSP Synthesis," IEEE Transactions on Computer Aided Design
of Integrated Circuits And Systems, 12(7), July 1993,
pp. 10631068

N.R. Shanbhag,
and K.K. Parhi,
"Relaxed LookAhead Pipelined LMS Adaptive Filters and
Their Application to ADPCM Coder," IEEE Transactions on Circuits and
Systems, Part II: Analog and Digital Signal Processing, Vol. 40(12),
December 1993, pp. 753766
1992

K.K. Parhi, C.Y.
Wang, A.P. Brown,
"Synthesis of Control Circuits in Folded Pipelined DSP
Architectures," IEEE Journal of Solid State Circuits, Vol. 27,
No. 1, January 1992, pp. 2943

M. Hatamian and
K.K. Parhi,
"An 85MHz FourthOrder Programmable IIR Digital Filter Chip,"
IEEE Journal of Solid State Circuits, Vol. 27, No. 2, February
1992, pp. 175183

H.R. Srinivas,
and K.K. Parhi,
"HighSpeed VLSI Arithmetic Processor Architectures Using
Hybrid Number Representation," Journal of VLSI Signal Processing,
Vol. 4, No. 2/3, 1992, pp. 177198

H.R. Srinivas,
and K.K. Parhi,
"A Fast VLSI Adder Architecture," IEEE Journal of Solid
State Circuits, Vol. 27, No. 5, May 1992, pp. 761767

K.K. Parhi,
"HighSpeed
VLSI Architectures for Huffman and Viterbi Decoders," IEEE Trans. on
Circuits and Systems, Part II: Analog and Digital Signal Processing,
Vol. 39, No. 6, June 1992, pp. 385391

K.K. Parhi,
"Video
Data Format Converters Using Minimum Number of Registers," IEEE Transactions
on Circuits and Systems For Video Technology, Vol. 2, No. 2,
June 1992, pp. 255267

K.K. Parhi,
"Systematic Synthesis of DSP Data Format Converters using LifeTime Analysis and ForwardBackward
Register Allocation," IEEE Trans. on Circuits and Systems,
Part II: Analog and Digital Signal Processing, Vol. 39,
No. 7, July 1992, pp. 423440
1991

K.K. Parhi, and
D.G. Messerschmitt,
"Static RateOptimal Scheduling of Iterative Data Flow
Programs via Optimum Unfolding,"
IEEE Trans. on Computers, Vol.
40(2), February 1991, pp. 178195

K.K. Parhi,
"A Systematic Approach for Design of DigitSerial Signal Processing Architectures,"
IEEE Trans. on Circuits and Systems, Vol. 38, No. 4, April
1991, pp. 358375

K.K. Parhi,
"Pipelining In Dynamic Programming Architectures," IEEE Trans. on Signal Processing,
Vol. 39, No. 6, June 1991, pp. 14421450

K.K. Parhi,
"Finite Word Effects in Pipelined Recursive Filters," IEEE Trans. on Signal
Processing, Vol. 39, No. 6, June 1991, pp. 14501454

K.K. Parhi,
"Pipelining in Algorithms with Quantizer Loops," IEEE Trans. on Circuits and Systems,
Vol. 38, No. 7, July 1991, pp. 745754

K.K. Parhi,
"Technology for the 90s: VLSI Signal and Image Processing Systems," IEEE Circuits
and Devices Magazine (special technology forecast issue), 7(4),
July 1991 (invited article), pp. 1617

K.K. Parhi, "Research
on VLSI For Digital Video Systems in Japan", Asian Scientific Information
Bulletin of the Office of Naval Research Office, 16(4), October
 December 1991, pp. 9398
1989

K.K. Parhi, and
D.G. Messerschmitt,
"Concurrent Architectures for TwoDimensional Recursive
Digital Filtering," IEEE Trans. on Circuits and Systems, Vol.
CAS36(6), June 1989, pp. 813829

K.K. Parhi, and
D.G. Messerschmitt,
"Pipeline Interleaving and Parallelism in recursive
Digital Filters, Part I: Pipelining using Scattered LookAhead and Decomposition,"
IEEE Transactions on Acoustics, Speech, and Signal Processing, Vol.
37(7), July 1989, pp. 10991117

K.K. Parhi, and
D.G. Messerschmitt,
"Pipeline Interleaving and Parallelism in recursive
Digital Filters, Part II: Pipelined Incremental Block Filtering,"
IEEE Transactions on Acoustics, Speech, and Signal Processing, Vol.
37(7), July 1989, pp. 11181135

K.K. Parhi,
"Algorithm Transformation Techniques for Concurrent Processors," Proceedings
of the IEEE, Special Issue on Supercomputer Technology, Vol. 77(12),
December 1989, pp. 18791895
1987

K.K. Parhi and
D.G. Messerschmitt,
"Concurrent Cellular VLSI Adaptive Filter Architectures,"
IEEE Transactionson Circuits and Systems, Vol. CAS34, No.
10, October 1987, pp. 11411151

K.K. Parhi and
R.S. Berkowitz,
"On Optimizing Importance SamplingSimulations," IEEE
Transactions of Circuits and Systems, Vol. CAS34, No. 12, December
1987, pp. 15581563
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