LDPC Decoders
Overview
Our research efforts in this area are directed towards designing low-cost LDPC decoder/encoder architectures for high throughput applications. To this end, we have proposed a joint code and decoder methodology leading to a high-speed (3,k)-regular LDPC code partly parallel decoder architecture, based on which we have implemented a 9216-bit, rate-1/2 (3,6)-regular LDPC code decoder on Xilinx FPGA device. The proposed (3,k)-regular LDPC codes have quasi-cyclic (QC) property and high girth so that it can be exploited by partly parallel decoder architecture and also results in a systematic efficient-encoding scheme. We have developed overlapping method of message passing decoding algorithm for a class of QC LDPC codes. By exploring the maximum concurrency of the two stages (check/variable node updates) using a novel scheduling algorithm, the decoding throughput could be increased by about twice. In addition, for a class of QC LDPC codes, a scheme using common hardware to compute both the two processing units has been proposed, which leads to about 21% area reduction of functional units part for a (3, 5)-regular LDPC code. Recently, we are developing LDPC codes and their low-cost decoder architectures for MB-OFDM UWB systems (IEEE 802.15.3a), and high-throughput WLAN (IEEE 802.11n). We have showed that the transmission distance of QC LDPC coded MB-OFDM UWB systems can increase by 29%-73% compared with that of convolutional codes.
Related Papers
T. Zhang, Z. Wang and K. K. Parhi, "On Finite Precision Implementation of Low Density Parity Check Codes Decoder", Proc. of IEEE ISCAS'2001, pp. 202-205, Sydney, Australia, May 2001 T. Zhang and K. K. Parhi, "A Class of Efficient-Encoding Generalized Low-Density Parity-Check Codes", Proc. of IEEE ICASSP'2001, pp. 2477-2480, Salt Lake City, UT, May 2001 T. Zhang and K. K. Parhi, "VLSI Implementation-Oriented (3,k)-Regular Low-Density Parity-Check Codes", IEEE Workshop on Signal Processing Systems (SiPS) 2001, pp. 25-36, Antwerp, Belgium, Sept. 2001 T. Zhang and K. K. Parhi, "High-Performance, Low-Complexity Decoding of Generalized Low-Density Parity-Check Codes", Proc. of Globecom'2001, Vol. 1, pp. 181-185, San Antonio, TX, Nov. 2001 T. Zhang and K. K. Parhi, “Joint code and decoder design for implementation-oriented (3, k)-regular LDPC codes”, Proc. of 35th Asilomar Conf. Signals, Systems, and Computers, Pacafic Grove, CA, Nov. 2001 T. Zhang and K. K. Parhi, "A 54 Mbps (3,6)-Regular FPGA LDPC Decoder", IEEE Workshop on Signal Processing Systems (SiPS) 2002, pp. 127-132, San Diego, CA, Oct. 2002 T. Zhang and K.K. Parhi, "An FPGA Implementation of (3,6) Regular Low-Density Parity-Check Code Decoder", Eurasip Journal on Applied Signal Processing, 2003(6), pp. 530-542, May 2003 T. Zhang and K. K. Parhi, “Joint (3,k)-regular LDPC code and decoder/encoder design”, IEEE Tans. Signal Processing, vol. 52, no. 4, pp. 1065–1079, April 2004 Z. Wang and Y. Chen and K. K. Parhi, “Area efficient decoding of quasi-cyclic low density parity check codes”, Proc. of IEEE ICASSP '04, Vol. V, pp. 49-52, May 2004 Y. Chen and K. K. Parhi, “Overlapped message passing for quasi-cyclic low-density parity check codes”, IEEE Trans. Circuits and Syst., vol. 51, pp. 1106-1113, June 2004 S. M. Kim and K. K. Parhi, “Overlapped decoding for a class of quasi-cyclic LDPC codes”, IEEE Workshop on Signal Processing Systems (SiPS) 2004, pp. 113-117, Sept. 2004 S. M. Kim and K. K. Parhi, “Quasi-Cyclic Low-Density Parity-Check Coded Multiband-OFDM UWB Systems”, Proc. of IEEE ISCAS’2005, pp. 65-68, May 2005 Back