TCAD Newsletter - January 2009 Issue
Placing you one click away from the best new CAD research!


Editorial
============= 

Macii, E. http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4723633&isnumber=4723629


Keynote Paper
=============

Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives
Marculescu, R.; Ogras, U. Y.; Peh, L.-S.; Jerger, N. E.; Hoskote, Y.
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4723644&isnumber=4723629

To alleviate the complex communication problems that arise as the number of
on-chip components increases, network-on-chip (NoC) architectures have been
recently proposed to replace global interconnects. This paper first provides a
general description of NoC architectures and applications. Then, it enumerates
several related research problems organized under five main categories:
Application characterization, communication paradigm, communication
infrastructure, analysis, and solution evaluation. Motivation, problem
description, proposed approaches, and open issues are discussed for each
problem from system, microarchitecture, and circuit perspectives. Finally, it
addresses the interactions among these research problems and put the NoC design
process into perspective.


Regular Papers
===============

Evaluating Pulling Effects in Oscillators Due to Small-Signal Injection
Maffezzoni, P.; D'Amore, D.
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4723643&isnumber=4723629

This paper presents a hybrid numerical-analytical approach to evaluate
injection pulling effects in RF oscillators. The method employs the Floquet
$v_1(t)$ eigenvector to project the perturbation signal into the phase-domain.
An original closed-form expression for the frequency-shift induced by
small-signal harmonic perturbations is derived. 


Analog Layout Generator for CMOS Circuits
Yilmaz, E.; Dundar, G.
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4723634&isnumber=4723629

In this work, a new layout level automation tool for analog CMOS circuits,
namely ALG, is presented.  ALG is not only designed to work as a stand alone
tool, it is also implemented to be the final step of an analog automation flow.
The flow supports circuit level specification in addition to layout level user
specifications, so that it can be integrated into an analog automation system.
Another feature of ALG is its interaction with a layout adviser tool, YASA.
YASA performs sensitivity simulations using a spice-like simulator providing
sensitivities of performance parameters with respect to circuit parameters.


Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low-Power Low-Cost Applications
Li, J.; Kang, K.; Roy, K.
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4723639&isnumber=4723629

This paper proposes a statistical simulation methodology to estimate parametric
variations in scaled LTPS TFT due to the inherent properties of the
polycrystalline material. To mitigate such variations, it proposes a
Multi-Finger (MF) design technique.


Frequent-Pattern-Guided Multilevel Decomposition of Behavioral Specifications
Molina, M. C.; Ruiz-Sautua, R.; Garcia-Repetto, P.; Hermida, R.
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4723642&isnumber=4723629

Conventional high-level synthesis algorithms treat specification operations as
atomic elements that are executed in one or several consecutive cycles and over
one functional unit. However, in most specifications there exist different
types, representations, and widths of operations that, handled at different
decomposition levels, may produce better designs. Most arithmetic operations
can be decomposed into smaller operations applying arithmetical properties.
Different decompositions can be performed to improve performance, or reduce the
area or power consumption. A pattern-based design methodology able to treat
every operation at its most appropriate decomposition level is proposed. It
produces reduced datapaths while meeting time constraints.


Signature-Based SER Analysis and Design of Logic Circuits
Krishnaswamy, S.; Plaza, S. M.; Markov, I. L.; Hayes, J. P.
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4723645&isnumber=4723629

This paper presents tools for logic-level Analysis of Soft Error Rate
(AnSER)and for Signature-based Design for Reliability (SiDeR). The authors use
signatures, i.e., partial truth-tables generated via bit-parallel functional
simulation, during soft error analysis and logic synthesis. The SER of a
circuit is closely related to testability measures such as signal probability
and observability. These measures are computed in linear time by AnSER using
signatures. SiDeR identifies and exploits redundancy already present in the
circuit to decrease SER with low area-overhead.


Variation-Aware Low-Power Synthesis Methodology for Fixed-Point FIR Filters
Choi, J. H.; Banerjee, N.; Roy, K.
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4723638&isnumber=4723629

This paper presents a novel FIR filter synthesis technique that allows
aggressive voltage scaling by exploiting the fact that all filter coefficients
are not equally important to the filter response. By specifying tighter
constraints (in terms of adders in the critical path) on the important
coefficients, it is ensured that the later computational steps compute only the
less important coefficients. In case of delay variations due to voltage
scaling/process variations, only the less important outputs are affected,
resulting in graceful degradation of filter quality. 


An Integer-Linear-Programming-Based Routing Algorithm for Flip-Chip Designs
Fang, J.-W.; Hsu, C.-H.; Chang, Y.-W
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4723647&isnumber=4723629

The flip-chip package provides a high chip-density solution to the demand for
more I/O pads of VLSI designs. This paper presents the first routing algorithm
in the literature for the pre-assignment flip-chip routing problem with a
pre-defined netlist among pads and wire-width and signal-skew considerations.
The algorithm presented is based on Integer Linear Programming and guarantees
to find an optimal solution for the addressed problem. 


Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs
Bahukudumbi, S.; Chakrabarty, K.
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4723640&isnumber=4723629

This paper presents methods for test-access mechanism (TAM) optimization and
test-length selection for wafer-level testing of core-based digital SoCs.  It
includes an optimization framework based on integer linear programming,
nonlinear programming, geometric programming, and fast heuristic methods. The
objective is to design a TAM architecture and determine test-lengths for the
embedded cores such that the overall SoC defect screening probability at wafer
sort is maximized. Defect probabilities for the embedded cores, obtained using
statistical yield modeling, are incorporated in the optimization framework. 


Functional Broadside Tests Under an Expanded Definition of Functional Operation Conditions
Pomeranz, I.; Reddy, S. M.
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4723637&isnumber=4723629

The definition of functional operation of a circuit is expanded to include all
the state-transitions that may be traversed during the application of a
synchronizing sequence. This is advantageous when functional broadside tests
are used to avoid overtesting. The effect of the expanded definition on the
coverage of transition faults is studied.


Non-Gaussian Statistical Timing Analysis Using Second-Order Polynomial Fitting
Cheng, L.; Xiong, J.; He, L.
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4723641&isnumber=4723629

Most of the existing SSTA techniques have difficulty in handling the
non-Gaussian variation distribution and non-linear delay variation model. This
paper, first proposes a new method to approximate the max operation of two
non-Gaussian random variables through second-order polynomial fitting. With
such approximation, it presents a new non-Gaussian SSTA algorithm. All the
atomic operations of the algorithms are performed by closed-form formulas,
hence they scale well for large designs. 


An On-the-Fly Parameter Dimension Reduction Approach to Fast Second-Order Statistical Static Timing Analysis
Feng, Z.; Li, P.; Zhan, Y.

http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4723648&isnumber=4723629
Accurate second-order SSTA techniques have been proposed to improve the
analysis accuracy, but at the cost of high computational complexity. This paper
addresses the analysis complexity brought by high parameter dimensionality in
statistical static timing analysis and proposes an accurate yet fast
second-order SSTA algorithm based upon novel on-the-fly parameter dimension
reduction techniques.  


Short Papers
============

Strengthening Model Checking Techniques With Inductive Invariants
Cabodi, G.; Nocco, S.; Quer, S.
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4723646&isnumber=4723629

This paper describes optimized techniques to efficiently compute and reap
benefits from inductive invariants within satisfiability (SAT)-based model
checking. The authors address sequential circuit verification and consider both
equivalences and implications between pairs of nodes in the logic networks.
First, they present a very efficient dynamic procedure, based on equivalence
classes and incremental SAT, specifically oriented to reduce the set of checked
invariants. Then, they show how to effectively integrate the computation of
inductive invariants within state-of-the-art SAT-based model-checking
procedures. 


Access-Pattern-Aware On-Chip Memory Allocation for SIMD Processors
Chang, H.; Sung, W.
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4723635&isnumber=4723629

The cycle count for each external memory access in SIMD (Single Instruction
Multiple Data) processors is heavily affected by the access pattern, such as
aligned, unaligned, or stride.  This paper presents a high performance dynamic
on-chip memory allocation method for SIMD processors by considering the memory
access pattern as well as the access frequency.  A developed compiler framework
performs code analysis and profiling for the access pattern and the access
count.  The framework conducts dynamic on-chip memory allocation but also
generates optimized codes.