TCAD Newsletter - February 2009 Issue
Placing you one click away from the best new CAD research!


Regular Papers
===============

Leveraging Local Intracore Information to Increase Global Performance in Block-Based Design of Systems-on-Chip
Li, C.-H.; Carloni, L. P.
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4757329&isnumber=4757328

This paper presents a novel performance optimization technique for latency
insensitive designs (LID). The approach takes advantage of the "functional
independence conditions" (FIC) of IP cores and applies it to the design of the
shell interface circuits of LID to improve the system-level performance by
avoiding unnecessary stalling. 

Improving Simulated Annealing-Based FPGA Placement With Directed Moves
Vorwerk, K.; Kennings, A.; Greene, J. W.
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4757337&isnumber=4757328

Simulated-annealing remains a widely-used heuristic for FPGA placement due, in
part, to its ability to produce high-quality placements while accommodating
complex objective functions.  This work discusses enhancements to
annealing-based placement which improve upon both quality and run-time.
Specifically, intelligent strategies for selecting and placing cells are
interspersed with traditional, random moves during an anneal, allowing the
annealer to converge more quickly and to attain better quality with less
statistical variability.
 
A Novel Wire-Density-Driven Full-Chip Routing System for CMP Variation Control
Chen, H.-Y.; Chou, S.-J.; Wang, S.-L.; Chang, Y.-W.
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4757345&isnumber=4757328

As nanometer technology scales, the post-CMP topography variation control
becomes crucial for manufacturing closure. It is thus desirable to consider
wire-density uniformity during routing. This paper presents a full-chip
grid-based router considering wire density for reticle planarization
enhancement. To fully consider wire distribution, the router applies a novel
two-pass, top-down planarity-driven routing framework, which employs new
density critical area analysis based on Voronoi diagrams and incorporates an
intermediate stage of density-driven layer/track assignment based on
incremental Delaunay triangulation. 

Substrate Topological Routing for High-Density Packages
Liu, S.; Chen, G.; Jing, T. T.; He, L.; Zhang, T.; Dutta, R.; Hong, X.-L.
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4757343&isnumber=4757328

This paper explains why planar routing is still required with multiple routing
layers for substrate routing, and proposes a flexible via-staggering technique
to improve routability. Moreover, it develops an efficient yet effective
substrate routing algorithm, applying dynamic pushing to tackle the net
ordering problem and reordering and rerouting to further reduce wire length and
congestion. 

Incremental Improvement of Voltage Assignment
Wu, H.; Wong, M. D. F.
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4757334&isnumber=4757328

The voltage island approach is effective for low power design. In this paper,
the authors propose a novel approach to improve the voltage assignment of
existing approaches by automatic outlier detection followed by incremental
placement. 

Synthesis and Optimization of Pipelined Packet Processors
Soviani, C.; Hadzic, I.; Edwards, S. A.
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4757341&isnumber=4757328

This paper considers pipelined packet processors built from modules connected
by FIFOs. It proposes a way to describe the modules, a synthesis algorithm, and
an algorithm for computing buffer sizes. The model is natural for a network
protocol designer.  The synthesis tool generates a circuit that processes
packets by words.  The analysis technique computes the maximum throughput of
each module then determines the smallest buffer sizes necessary. 

Timing-Aware Multiple-Delay-Fault Diagnosis
Mehta, V. J.; Marek-Sadowska, M.; Tsai, K.-H.; Rajski, J.
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4757344&isnumber=4757328

This paper analyzes the multiple-delay-fault diagnosis problem and proposes a
novel approach to solve it. In addition, it enhances the diagnostic resolution
by processing failure logs at various slower-than-nominal clock frequencies.
Finally, it evaluates the utility of n-detection and timing-aware ATPG sets. 

Deviation-Based LFSR Reseeding for Test-Data Compression
Wang, Z.; Fang, H.; Chakrabarty, K.; Bienek, M.
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4757336&isnumber=4757328

This paper shows how the output deviations of test patterns can be used as a
metric to select appropriate LFSR seeds for reseeding-based test compression. 

Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging
Jiang, T.-Y.; Liu, C.-N. J.; Jou, J.-Y.
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4757342&isnumber=4757328

Existing approaches for HDL debugging attempt to extract a reduced set of error
candidates to speed up the HDL debugging. However, finding true design errors
in the derived set still consumes much time. Objective of this work is to
develop a new Probabilistic Confidence Score (PCS) to provide more reliable and
accurate debugging priority w.r.t. existing approaches.

Algorithms for State Restoration and Trace-Signal Selection for Data Acquisition in Silicon Debug
Ko, H. F.; Nicolici, N.
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4757338&isnumber=4757328

To locate and correct design errors that escape pre-silicon verification,
silicon debug has become a necessary step in the implementation flow of digital
integrated circuits. Embedded logic analysis, which employs on-chip storage
units to acquire data in real-time from the internal signals of the
circuit-under-debug, has emerged as a powerful technique for improving
observability during in-system debug. This paper presents accelerated
algorithms for restoring circuit state elements from the traces collected
during a debug session.


Short Papers
===============

Dynamic Scan Chain Partitioning for Reducing Peak Shift Power During Test
Almukhaizim, S.; Sinanoglu, O.
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4757340&isnumber=4757328

This paper proposes a dynamic partitioning approach capable of adapting to the
transition distribution of any test pattern, and thus of delivering
near-perfect peak power reductions. The proposed dynamic partitioning hardware
allows for the partitioning reconfiguration on a per test pattern basis, hence
delivering a solution that is test set independent.