TCAD Newsletter - April 2009 Issue Placing you one click away from the best new CAD research! Regular Papers ============== Extended Sequential Logic for Synchronous Circuit Optimization and Its Applications Meher, P. K. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4802227&isnumber=4802215 In this paper, the authors present a new approach for the extension of sequential logic functionality of D flip-flop in order to perform an additional Boolean function simultaneously along with its usual bit-storage function. Low-Power Fanout Optimization Using Multi Threshold Voltages and Multi Channel Lengths Amelifard, B.; Fallah, F.; Pedram, M. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4802217&isnumber=4802215 This paper addresses the problem of low-power fanout optimization for near-continuous size inverter libraries. It is demonstrated that because of neglecting short-circuit current, previous techniques proposed to optimize the area of a fanout tree may result in excessive power consumption. The paper describes an efficient method to minimize the total power consumption of a fanout tree by using multi channel length and multi threshold voltage techniques. A Parallel Harmonic-Balance Approach to Steady-State and Envelope-Following Simulation of Driven and Autonomous Circuits Dong, W.; Li, P. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4802232&isnumber=4802215 This paper presents a parallel harmonic balance approach for steady-state and envelope-following analyses of both driven and autonomous circuits, which is centered on a naturally-parallelizable preconditioning technique to speedup the core computation in harmonic balance. As a coarse-grained approach, it facilitates parallel computing and simplifies parallel programming. Algorithms for Automatic Model Topology Formulation Feng, Y.; Mantooth, H. A. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4802233&isnumber=4802215 This paper presents a novel algorithm for automatic behavioral model topology formulation (MTF). It includes the determining the controllability and equivalence of branches, identifying differential pairs and current mirror structures and extracting a subset of nodes in circuits that is important to rebuild the behavior of the original circuit while the other nodes will be collapsed. This algorithm is implemented in a fully automated modeling tool, ASCEND, which starts from the netlist description of a circuit and generates a differential algebraic equation (DAE) based model. Harmonic-Balance Algorithms for the Circuit-Level Nonlinear Analysis of UWB Receivers in the Presence of Interfering Signals Rizzoli, V.; Mastri, F.; Costanzo, A.; Masotti, D. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4802216&isnumber=4802215 Circuit-level analysis of pulse-UWB receivers in the presence of interfering signals is developed. The procedure is based on model-order reduction harmonic-balance technique devised to handle very large signal spectra. Simplifying assumptions typical of system-level approaches are overcome allowing rigorous and efficient computation of interference effects on UWB receivers nonlinear regime. Archer: A History-Based Global Routing Algorithm Ozdal, M. M.; Wong, M. D. F. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4802223&isnumber=4802215 In this paper, a new global routing algorithm Archer is proposed. The basic idea is to guide the routing iterations out of local optima through effective usage of congestion histories during rip-up and reroute. Also, the problem of how to enable a smooth trade-off between seemingly conflicting objectives of overflow and wirelength minimization is studied in this paper. Furthermore, a Lagrangian relaxation based bounded-length min-cost topology improvement algorithm is proposed for the purpose of congestion optimization. Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise Enami, T.; Ninomiya, S.; Hashimoto, M. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4802231&isnumber=4802215 Power supply noise is having increasingly more influence on timing. This paper proposes static timing analysis that considers power supply noise where the dependence of noise on input vectors and spatial and temporal correlations are handled statistically. The authors construct a statistical model of power supply voltage, and demonstrate that power-voltage variations are highly correlated and adopting principal component analysis as an orthogonalization technique can effectively reduce the number of variables. Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications Cho, D.; Pasricha, S.; Issenin, I.; Dutt, N. D.; Ahn, M.; Paek, Y. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4802221&isnumber=4802215 Exploiting runtime memory access traces can be a complementary approach to compiler optimizations for the energy reduction in memory hierarchy. This is particularly important for emerging multimedia applications since they usually have input-sensitive runtime behavior which results in dynamic and/or irregular memory access patterns. These types of applications are normally hard to optimize by static compiler optimizations. The reason is that their behavior stays unknown until runtime and may even change during computation. To tackle this problem, this work presents an integrated approach of software and hardware techniques to exploit data reusability of multimedia applications in Multi-Processor SoCs. An Analytical Dynamic Scaling of Supply Voltage and Body Bias Based on Parallelism-Aware Workload and Runtime Distribution Kim, J.; Oh, S.; Yoo, S.; Kyung, C.-M. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4802230&isnumber=4802215 Dynamic voltage and frequency scaling (DVFS) for a parallel software program is crucial for lowering the power consumption of multi-processor systems-on-a-chips. This paper proposes an analytical DVFS method that exploits slack by considering the varying parallelism over each path in a task graph. It yields minimum average energy consumption by utilizing the runtime distribution of a software program while satisfying the deadline constraints. The proposed method tackles both dynamic and leakage power consumption by combined Vdd/Vbb scaling. Evaluation of Analog/RF Test Measurements at the Design Stage Stratigopoulos, H.-G.; Mir, S.; Bounceur, A. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4802222&isnumber=4802215 This paper presents a method to evaluate analog/RF test measurements at the design stage which can handle process variations. The method can be readily used to estimate test metrics with parts per million accuracy and to fix test limits that satisfy specific trade-offs between metrics of interest. Design and Synthesis of Programmable Logic Block With Mixed LUT and Macrogate Hu, Y.; Das, S.; Trimberger, S.; He, L. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4802234&isnumber=4802215 It is unclear whether incorporating macro-gates with wide inputs inside PLBs is beneficial to FPGAs. In this paper, the authors first develop a methodology to extract a small set logic functions that are able to implement a large portion of functions for given FPGA applications, and propose a heterogeneous PLB with one LUT and one macro-gate for the selected logic functions. Furthermore, they develop a synthesis flow for such heterogeneous PLBs. Short Papers ============ An Improved Soft-Error Rate Measurement Technique Sanyal, A.; Ganeshpure, K.; Kundu, S. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4802228&isnumber=4802215 Soft errors (SER) are measured in Failure-In-Time (FIT) rate that represents the number of fails encountered per billion hours of operation. FIT rate measurement is time consuming and requires accelerated testing. This paper describes a technique for ranking soft error prone nodes based on electrical analysis which is used to drive a pattern generator that maximizes the likelihood of detecting a soft error. A design-for-testability approach to support test-per-clock operation is also described that eliminates the overhead of scan shifting. Analysis of Deskew Signaling Via Adaptive Timing Wang, S.; Wang, L. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4802229&isnumber=4802215 This paper presents an adaptive timing method for analysis of deskew signaling in high-performance integrated systems. The proposed approach models the practical deskew schemes as an adaptive system to study the performance limit of deskew signaling. The authors investigate the statistical properties of optimal deskew, which can be considered as the theoretical limit of deskew signaling.