TCAD Newsletter - June 2009 Issue
Placing you one click away from the best new CAD research!

Keynote Paper
=============

An Outlook on Design Technologies for Future Integrated Systems
De Micheli, G.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4957592&isnumber=4957591

The economic and social demand for ubiquitous and multifaceted electronic
systems - in combination with the unprecedented opportunities provided by the
integration of various manufacturing technologies - is paving the way to a new
class of heterogeneous integrated systems, with increased performance and
connectedness and providing us with gateways to the living world. This article
surveys design requirements and solutions for heterogeneous systems and
addresses design technologies for realizing them.


Regular Papers
==============

Analog Placement Based on Symmetry-Island Formulation
Lin, P.-H.; Chang, Y.-W.; Lin, S.-C.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4957593&isnumber=4957591

This paper presents a linear-time packing algorithm for analog placement with
symmetry constraints based on the automatically symmetric-feasible B*-tree, the
hierarchical B*-tree, and the symmetry-island formulation. Unlike the previous
works, the proposed approach can place the symmetry modules in a symmetry group
in close proximity and significantly reduce the search space. 


A Transform-Parametric Approach to Boolean Matching
Agosta, G.; Bruschi, F.; Pelosi, G.; Sciuto, D.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4957594&isnumber=4957591

In this paper, the problem of P-equivalence Boolean matching is addressed,
defining a formal framework that unifies some of the spectral and canonical
form-based approaches to the problem. After showing that these approaches are
particular cases of a single generic algorithm, parametric with respect to a
transformation of the input function, a linear transformation that
significantly speeds up Boolean matching with respect to the state of the art
is designed. 


Gate Sizing for Cell-Library-Based Designs
Hu, S.; Ketkar, M.; Hu, J.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4957595&isnumber=4957591

Discrete gate sizing for cell library-based design methodologies has become
increasingly important in the prevailing VLSI design. In this paper, a
continuous solution guided dynamic programming-like algorithm is proposed for
the discrete gate sizing problem. A set of novel techniques, such as Locality
Sensitive Hashing based solution pruning, are also proposed to accelerate the
algorithm. 


Modeling and Experimental Measurement of Active Substrate-Noise Suppression in Mixed-Signal 0.18-um BiCMOS Technology
Dai, H.; Knepper, R. W.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4957596&isnumber=4957591

Simulation and experimental results are presented for an active noise
suppression technique to reduce substrate crosstalk in mixed-signal IC
technology. The method utilizes a 3D distributed substrate model, along with a
BiCMOS noise suppression amplifier designed in IBM's 0.18-µm BiCMOS technology.
BF-Moat and P+/DT/NW GR isolation structures were also integrated into the 3D
substrate model, for investigation of their isolation ability. 


Resistance Estimation for Lateral Power Arrays Through Accurate Netlist Generation
Das, S.; Sural, S.; Patra, A.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4957597&isnumber=4957591

This paper presents an efficient technique for estimation of resistance of a
large lateral power array layout along with parasitics. We extract a resistive
network for metalizations utilizing the Finite Element Method (FEM). The method
primarily benefits in terms of computational speed from re-use methodology
facilitated by repetitive structure of the metal interconnect layers. Device
channels are modeled by linear resistances as the power MOS operates mostly in
the linear region. 


Inductance and Resistance Calculations in Three-Dimensional Packaging Using Cylindrical Conduction-Mode Basis Functions
Han, K. J.; Swaminathan, M.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4957598&isnumber=4957591

For the successful electrical design of system-in-package, this paper proposes
an efficient method for extracting wide-band resistance and inductance from a
large number of 3D interconnections. The proposed method uses the modal
equivalent network from electric field integral equation with cylindrical
conduction mode basis function, which reduces the matrix size for large 3D
interconnection problems. Additional enhancement schemes proposed further
reduce the cost for computing the partial inductances.


Multiscale Thermal Analysis for Nanometer-Scale Integrated Circuits
Hassan, Z.; Allec, N.; Shang, L.; Dick, R. P.; Venkatraman, V.; Yang, R.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4957599&isnumber=4957591

Thermal analysis has long been essential for designing reliable,
high-performance, cost-effective ICs. Characterizing the thermal profile of an
IC quickly enough to allow feedback on the thermal effects of tentative design
changes is a daunting problem, and its complexity is increasing. In this work,
the authors propose and develop ThermalScope, a multi-scale thermal analysis
method for nanometer-scale IC design. It unifies microscopic and macroscopic
thermal modeling methods, and supports adaptive multi-resolution modeling.
ThermalScope is designed for full-chip thermal analysis of billion-transistor
nanometer-scale IC designs, with accuracy at the scale of individual devices.


Full-Chip Model for Leakage-Current Estimation Considering Within-Die Correlation
Heloue, K. R.; Azizi, N.; Najm, F. N.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4957600&isnumber=4957591

This paper presents an efficient technique for finding the leakage statistics
of a candidate design while considering process variations spatial
correlations. The model uses a "random gate" concept to capture high-level
characteristics of a candidate chip design, which are sufficient to determine
its leakage. The authors show that, for large gate count, the set of all
designs that share the same high-level characteristics have approximately the
same leakage. 


Optimal Design of the Power-Delivery Network for Multiple Voltage-Island SoCs 
Amelifard, B.; Pedram, M.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4957601&isnumber=4957591

This paper introduces techniques for power efficient design of power delivery
network in multiple voltage-island SoC designs. In the first part of this paper
it is shown that in a SoC design with static voltage assignment, a multi-level
tree topology of suitably chosen DC-DC converters between the power source and
loads can result in higher power efficiency in the power delivery network. In
the second part of the paper, a new technique is presented to design the power
delivery network for a SoC design to support dynamic voltage scaling. 


Using Data Compression for Increasing Memory System Utilization
Ozturk, O.; Kandemir, M.; Irwin, M. J.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4957602&isnumber=4957591

Memory system presents one of the critical challenges in embedded system design
and optimization. While it is true that the on-chip memory capacity of embedded
systems is continuously increasing, the increases in the complexity of embedded
applications and the sizes of the datasets they process are far greater.
Motivated by this observation, this paper presents and evaluates a
compiler-driven approach to data compression for reducing memory space
occupancy. This problem is first studied in the context of single core systems
and later extended to MPSoCs where compressions and decompressions are
scheduled intelligently such that they do not conflict with execution.


Testing Resistive Opens and Bridging Faults Through Pulse Propagation
Favalli, M.; Metra, C.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4957603&isnumber=4957591

This paper addresses the detection of resistive open and bridging faults that
lie out of the most critical paths. These faults cannot be detected by delay
fault testing using the nominal clock frequency because the induced delay
defects are not large enough to result in timing violations. However, they may
give rise to reliability problems. To detect them, a testing method is proposed
that exploits the degraded capability of faulty paths to propagate pulses. 



Short Papers
============

Topology Synthesis of Cascaded Crossbar Switches
Jun, M.; Yoo, S.; Chung, E.-Y.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4957604&isnumber=4957591

Performance requirements of on-chip network increase as SoCs are becoming more
and more complex. For high performance applications, crossbar switch-based
networks are replacing the traditional shared buses as the backbone networks in
SoCs. This paper tackles the topology design of on-chip networks with crossbar
switches in a cascaded fashion. It also resolves the unacceptable complexity of
the previous method based on mixed integer linear programming by a heuristic
method.