TCAD Newsletter - July 2009 Issue
Placing you one click away from the best new CAD research!


Special Section
=============

Challenges and Solutions in the Development of Automotive Systems
Sangiovanni-Vicentelli, A.; Di Natale, M.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5075804&isnumber=5075803

This special section on automotive systems collects four of the presentations
given on a special day at the DATE'08 Conference, held in Munich, Germany, in
April 2008.


The Tire as an Intelligent Sensor
Ergen, S. C.; Sangiovanni-Vincentelli, A.; Sun, X.; Tebano, R.; Alalusi, S.; Audisio, G.; Sabatini, M.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5075807&isnumber=5075803

Active safety systems are based upon the accurate and fast estimation of the
value of important dynamical variables such as forces, load transfer, actual
tire-road friction (kinetic friction), and maximum tire-road friction available
(potential friction). Measuring these parameters directly from tires offers the
potential for improving significantly the performance of active safety systems.
This paper presents a distributed architecture for a data acquisition system
that is based on a number of complex intelligent sensors inside the tire that
form a wireless sensor network with coordination nodes placed on the car's
body. 


From a Federated to an Integrated Automotive Architecture
Obermaisser, R.; El Salloum, C.; Huber, B.; Kopetz, H.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5075819&isnumber=5075803

This paper describes an architecture for automotive systems based on multi-core
SoCs. The authors integrate functions from different suppliers into a few ECUs
using a dedicated core for each function. This work is fueled by technological
opportunities of advances in the semiconductor industry and the challenges of
providing dependable automotive systems at competitive costs. The presented
architecture introduces infrastructure IP cores to overcome key challenges in
moving to automotive multi-core SoCs: a time-triggered network-on-a-chip with
fault isolation, a diagnostic IP core for error detection and state recovery, a
gateway IP core for legacy systems, and an IP core for reconfiguration.


Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-Critical Embedded Systems
Wilhelm, R.; Grund, D.; Reineke, J.; Schlickling, M.; Pister, M.; Ferdinand, C.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5075820&isnumber=5075803

Embedded hard real-time systems need reliable guarantees for the satisfaction
of their timing constraints. Experience with the use of static timing analysis
methods and the tools based on them in the automotive and the aeronautics
industries is positive. This dependence on the architectural development is of
growing concern to the developers of timing analysis tools and their customers,
the developers in industry. This article describes the architectural influence
on static timing analysis and gives recommendations as to profitable and
unacceptable architectural features.


System Level Performance Analysis for Real-Time Automotive Multicore and Network Architectures
Schliecker, S.; Rox, J.; Negrean, M.; Richter, K.; Jersak, M.; Ernst, R.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5075823&isnumber=5075803

This paper surveys existing performance analysis approaches from real-time
systems research and compares them to the established layered software
architectures of automotive system design. The paper highlights key challenges
for the application of performance analysis in this domain and identifies
structural as well as behavioral "modeling gaps". While structural gaps can be
overcome by model transformations, behavioral gaps require real extensions. Two
such extensions are discussed in detail, namely the use of hierarchical event
models and the specialties of timing analysis for multi-core platforms. The
paper concludes with comparisons of the analysis techniques, both technically
and concerning their industrial applicability.



Regular Papers
==============

Low-Cost Characterization and Calibration of RF Integrated Circuits through IQ Data Analysis
Acar, E.; Ozev, S.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5075813&isnumber=5075803

Due to the increasing complexity of Radio Frequency (RF) circuits, their
testing becomes more challenging.  This paper presents a low cost test
methodology that determines significant performance parameters, such as path
gain, quadrature imbalances, noise, bit error rate (BER), and error vector
magnitude (EVM) through a single test setup. Simulation and measurement results
indicate that these performance parameters can be calculated and estimated
accurately through a single test set-up and using a shorter test sequence than
required by traditional techniques. In addition, a calibration technique is
presented for single carrier systems to recover marginally failing devices
through analytically correcting performance parameters.


ELIAD: Efficient Lithography Aware Detailed Routing Algorithm With Compact and Macro Post-OPC Printability Prediction
Cho, M.; Yuan, K.; Ban, Y.; Pan, D. Z.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5075817&isnumber=5075803

This paper presents ELIAD, an efficient lithography aware detailed router to
enhance silicon image after OPCin a correct-by-construction manner. The author
first show that a pre-OPC litho-metric is uncorrelated with a post-OPC metric,
which stresses  a post-OPC litho-metric for design-time optimization. Then,
they propose a post-OPC litho-metric for a detailed router based on statistical
characterization where the interferences among litho-prone shapes are captured
as a lookup table. 


A Framework for Energy-Consumption-Based Design Space Exploration for Wireless Sensor Nodes
Chouhan, S.; Bose, R.; Balakrishnan, M.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5075821&isnumber=5075803

In sensor nodes, operating over "small" distances, both computation and radio energy influence the battery life. In such a scenario, to evaluate utility of error correcting codes (ECCs) from energy perspective, one has to consider energy consumed in encoding-decoding and transmitting additional ``redundant'' bits vis-a-vis the energy saved due to coding gain. This paper presents a framework for evaluating various ECCs based on a comprehensive energy model of a sensor node.  The exploration results show that as compared to the uncoded data transmission, the energy optimal ECC saves 15-60% node energy for the given parameters.


Power Optimization With Power Islands Synthesis
Dal, D.; Mansouri, N.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5075810&isnumber=5075803

With migration to DSM technologies, power has come to the forefront of concerns
and as a result, the power has become a critical design parameter. This work
presents a novel High-Level Synthesis methodology that eliminates the Spurious
Switching Activity and the leakage in a great portion of the resulting circuit
by partitioning it into islands. Each island is a cluster of logic whose power
can be controlled independent from the rest of the circuit, and hence can be
completely powered down when all of the logic it contains is idling.


A Generic Data-Driven Nonparametric Framework for Variability Analysis of Integrated Circuits in Nanometer Technologies
Mukhopadhyay, S.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5075822&isnumber=5075803

This paper presents a generic data-driven non-parametric analyzer (GDNA) to
estimate the impact of process variations on device properties and circuit
functionalities in nanometer technologies. The framework of GDNA uses a kernel
estimator which eliminates the need for a-priori assumption of the nature of
variation. A tail probability estimator uses the kernel estimator to predict
low occurrence probabilities using a small set of observed samples. 


Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate
Srivastava, N.; Suaya, R.; Banerjee, K.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5075816&isnumber=5075803

This paper proposes an efficient method to accurately compute the
frequency-dependent impedance of VLSI interconnects in the presence of
multi-layer conductive substrates. The resulting accuracy (errors less than 3%)
and CPU time reduction (more than an order of magnitude) emerge from three
different ingredients: a 2-D Green's function approach with the correct
quasi-static limit, a modified discrete complex images approximation to the
Green's function, and a continuous dipole expansion to evaluate the magnetic
vector potential at the short distances relevant to VLSI interconnects. 


A Novel Table-Based Approach for Design of FinFET Circuits
Thakker, R. A.; Sathe, C.; Sachid, A. B.; Shojaei Baghini, M.; Ramgopal Rao, V.; Patil, M. B.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5075818&isnumber=5075803

A new LUT approach, based on normalization of the drain current with an ID-VG
template, is proposed for simulation of MOS transistor circuits. The LUT
approach is validated by considering two examples and comparing the LUT results
with mixed-mode simulation results. This approach is implemented in a circuit
simulator and integrated, for the first time, with an optimizer to enable
efficient design of circuits in novel technologies such as FinFET.  


Gate Sizing by Lagrangian Relaxation Revisited
Wang, J.; Das, D.; Zhou, H.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5075815&isnumber=5075803

In this paper, the authors formulate the generalized convex sizing (GCS)
problem that unifies the sizing problems and applies to sequential circuits
with clock-skew optimization. They revisit the approach to solve the sizing
problem by Lagrangian relaxation, point out several misunderstandings in the
previous paper, and extend the approach to handle general convex delay
functions in the GCS problems. They identify a class of proper GCS problems
whose objective functions in the simplified dual problem are differentiable and
transform the simultaneous sizing and clock-skew optimization problem into a
proper GCS problem. 


Adjustment-Based Modeling for Timing Analysis Under Variability
Xie, L.; Davoodi, A.; Zhang, J.; Wu, T.-H.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5075805&isnumber=5075803

This paper presents an adjustment-based modeling framework for timing analysis
under variability. Instead of building a complex model directly between the
circuit timing and parameter variability, we propose to build a model that
adjusts an approximate variation-aware timing into an accurate one. The idea is
that it is easier to build a model that adjusts an approximate estimate into an
accurate one. 



Short Papers
==============

Feasible Aggressor-Set Identification Under Constraints for Maximum Coupling Noise
Sinha, D.; Rubin, A.; Visweswariah, C.; Borkam, F.; Schaeffer, G.; Abbaspour, S.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5075811&isnumber=5075803

In this paper, the authors consider the problem of identifying a feasible set
of aggressor nets that would induce maximum crosstalk noise on a coupled victim
net, under switching constraints. They present a novel mathematical formulation
of this problem, and propose a Lagrangian Relaxation based approach for solving
it efficiently and optimally. 


Low-Power Scan Testing for Test Data Compression Using a Routing-Driven Scan Architecture
Xiang, D.; Hu, D.; Xu, Q.; Orailoglu, A.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5075812&isnumber=5075803

A new scan architecture is proposed to reduce peak test power and capture
power.  Only a subset of scan flip-flops is activated to shift test data or
capture test responses in any clock cycle. This can effectively reduce the
capture test power and peak test power. Two routing-driven schemes are
presented to reduce the routing overhead.


Inductance Extraction for Interconnects in the Presence of Nonlinear Magnetic Materials
Yi, Y.; Wenzel, R.; Sarin, V.; Shi, W.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5075825&isnumber=5075803

This paper presents a fast algorithm to extract inductance in the presence of
nonlinear magnetic materials. The algorithm models the nonlinear magnetic
characteristics by solving the Landau-Lifshitz-Gilbert equation, and the
nonhomogeneous magnetic characteristics by introducing the fictitious magnetic
charge. To speed up the algorithm, we apply a number of innovative techniques
including the approximation of magnetic charge effect and the modeling of
currents with solenoidal basis.