TCAD Newsletter - August 2009 Issue
Placing you one click away from the best new CAD research!


Regular Papers
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Dependent-Latch Identification in Reachable State Space
Lin, C.-H.; Wang, C.-Y.; Chen, Y.-C.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&isnumber=5166543&arnumber=5166585

The large number of latches in current digital designs increases the complexity
of formal verification and logic synthesis, since an increase in latch numbers
leads to an exponential expansion of the state space. This paper proposes an
approach to find the dependent latches in a sequential circuit by using SAT
solvers with the Craig interpolation theorem. With the information of dependent
latches, the state space can be reduced. 


Design Methodology for Low Power and Parametric Robustness Through Output-Quality Modulation: Application to Color-Interpolation Filtering
Banerjee, N.; Karakonstantis, G.; Choi, J. H.; Chakrabarti, C.; Roy, K.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&isnumber=5166543&arnumber=5166620

Power dissipation and process variation robustness have conflicting design
requirements. This paper presents a novel low-power variation tolerant
algorithm/architecture for color interpolation that allows graceful degradation
in PSNR under aggressive voltage scaling and/or extreme process variations.
This is achieved by exploiting the fact that all computations in pixel value
interpolation do not equally contribute to PSNR improvement. In presence of
Vdd-scaling and process variations, the architecture ensures that only the less
important computations are affected by delay failures. 


Time-Domain Orthogonal Finite-Element Reduction-Recovery Method for Electromagnetics-Based Analysis of Large-Scale Integrated Circuit and Package Problems
Chen, D.; Jiao, D.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&isnumber=5166543&arnumber=5166550

A time-domain orthogonal finite-element reduction-recovery method is developed
to overcome the large problem sizes encountered in the simulation of
large-scale integrated circuit and package problems. In this method, a set of
orthogonal prism vector basis functions are developed. Based on this set of
bases, an arbitrary three-dimensional multilayered system such as a combined
package and die is reduced to a single-layer system with negligible
computational cost. More important, the reduced single-layer system is
diagonal, and hence can be solved readily. 


Convergence of Transverse Waveform Relaxation for the Electrical Analysis of Very Wide Transmission Line Buses
Elfadel, I. M.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&isnumber=5166543&arnumber=5166597

This paper is a study of the convergence of the transverse waveform relaxation
(TWR) method for the analysis of very wide, on-chip multiconductor transmission
line systems.  Using a splitting framework for the per-unit-length RLGC matrix
parameters, it is shown that the TWR method generates a summable series of
iterated kernels with decreasing norms that converges to the state transition
matrix of the distributed conducting system.  As a result, fast convergence is
guaranteed, especially in the case of weak electromagnetic couplings. 


Template-Free Symbolic Performance Modeling of Analog Circuits via Canonical-Form Functions and Genetic Programming
McConaghy, T.; Gielen, G. G. E.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&isnumber=5166543&arnumber=5166638

This paper presents CAFFEINE, a method to automatically generate compact,
interpretable symbolic performance models of analog circuits with no prior
specification of an equation template.  CAFFEINE uses SPICE simulation data, to
model arbitrary nonlinear circuits and circuit characteristics.  CAFFEINE
expressions are canonical form functions: product-of-sum layers alternating
with sum-of-product layers, as defined by a grammar. Multi-objective genetic
programming trades off error with model complexity.  


Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events and Its Application to Memory Design
Singhee, A.; Rutenbar, R. A.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&isnumber=5166543&arnumber=5166555

Circuit reliability under random parametric variation is an area of growing
concern. For highly replicated circuits, e.g., static random access memories
(SRAMs), a rare statistical event for one circuit may induce a not-so-rare
system failure. Existing techniques perform poorly when tasked to generate both
efficient sampling and sound statistics for these rare events. Statistical
blockade is a novel Monte Carlo technique that allows to efficiently filter-to
block-unwanted samples that are insufficiently rare in the tail distributions
that are sought. The method synthesizes ideas from data mining and extreme
value theory and, for the challenging application of SRAM yield analysis, shows
speedups of 10-100 times over standard Monte Carlo.


Locality-Driven Parallel Power Grid Optimization
Zeng, Z.; Li, P.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&isnumber=5166543&arnumber=5166628

Large very large-scale-integration power/ground distribution networks are
challenging to analyze and design due to the sheer network complexity. In this
paper, a parallel sizing optimization approach is presented to minimize the
wiring area of a power grid while meeting $IR$ drop and electromigration
constraints. Motivated by a proposed two-level hierarchical optimization, this
paper presents a novel locality-driven partitioning scheme to allow for
divide-and-conquer-based scalable optimization of large power grids, which is
infeasible via flat optimization. 


A Framework for Scalable Postsilicon Statistical Delay Prediction Under Process Variations
Liu, Q.; Sapatnekar, S. S.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&isnumber=5166543&arnumber=5166631

Due to increased variability trends in nanoscale integrated circuits,
statistical circuit analysis and optimization has become essential.  While
statistical timing analysis has an important role to play in this process, it
is equally important to develop die-specific delay prediction techniques using
post-silicon measurements. This paper presents a novel method for post-silicon
delay analysis. The approach gathers data from a small number of on-chip test
structures, and combines this information with pre-silicon statistical timing
analysis to obtain narrow, die-specific, timing probability density function
(PDF).


System-Level Bus-Based Communication Architecture Exploration Using a Pseudoparallel Algorithm
Chiou, L.-Y.; Chen, Y.-S.; Lee, C.-H.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&isnumber=5166543&arnumber=5166607

With the common use of intellectual properties in SoC and the large amount of
data interchanges among IPs, communication architecture significantly affects
the system in terms of power and performance. Therefore, designers should
carefully plan the communication architecture to meet the power and performance
requirements. This work presents a pseudo parallel method for bus architecture
exploration at the system level to speedup the power and performance of
co-exploration time. 


A Universal Placement Technique of Compressed Instructions for Efficient Parallel Decompression
Qin, X.; Mishra, P.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&isnumber=5166543&arnumber=5166640

Existing instruction compression techniques provide either efficient
compression with slow decompression or fast decompression at the cost of
compression efficiency. This article combines the advantages of both approaches
by introducing a novel bitstream placement method to support parallel
decompression without sacrificing the compression efficiency. The approach
enables splitting a single bitstream fetched from memory into multiple
bitstreams, which are then fed into different decoders. As a result, multiple
decoders can work simultaneously to achieve high decode bandwidth. 


Two-Dimensional and Three-Dimensional Integration of Heterogeneous Electronic Systems Under Cost, Performance, and Technological Constraints
Weerasekera, R.; Pamunuwa, D.; Zheng, L.-R.; Tenhunen, H.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&isnumber=5166543&arnumber=5166634

This paper discusses realistic metrics appropriate for performance and cost
trade-off analyses both at the system conceptual level in the early stages of
the design cycle and in the implementation phase, for verification. In order to
validate the proposed metrics and methodology, two ubiquitous electronic
systems are analyzed under various implementation schemes and the performance
trade-offs discussed. 


Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip
Wang, Z.; Chakrabarty, K.; Wang, S.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&isnumber=5166543&arnumber=5166602

This paper presents an SoC testing approach that integrates test data
compression, TAM/test wrapper design, and test scheduling. An efficient LFSR
reseeding technique is used as the compression engine. Experimental results are
presented for ISCAS and IWLS benchmark circuits.



Short Papers
==============

Minimum-Period Register Binding
Huang, S.-H.; Cheng, C.-H.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&isnumber=5166543&arnumber=5166635

This paper points out that register binding in the high-level synthesis stage
has a significant impact on the clocking constraints between registers. As a
result, different register binding solutions often lead to different smallest
feasible clock periods. Based on that observation, the paper formally draws up
the problem of register binding for clock period minimization. 


Process Variation-Aware Test for Resistive Bridges
Ingelsson, U.; Al-Hashimi, B. M.; Khursheed, S.; Reddy, S. M.; Harrod, P.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&isnumber=5166543&arnumber=5166639

This paper analyses the behaviour of resistive bridging faults under process
variation. A detrimental impact on test quality is found in variation induced
test escapes. The impact is quantified by a novel test robustness metric and to
mitigate test escapes, a new process variation-aware test generation method is
presented. The method targets logic faults that combine high occurrence
probability with significant amounts of undetected bridge resistance because
they have high impact on test robustness. 


High-Speed Post-Layout Logic Simulation Using Quasi-Static Clock Event Evaluation
Kim, M.-J.; Chung, E.-Y.; Yoon, S.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&isnumber=5166543&arnumber=5166544

The post-layout gate-level simulation constitutes a critical step for timing
closure. The major drawback of traditional post-layout gate-level simulation is
its long analysis time. An alternative method is static timing analysis, which
can reduce analysis time. However it sacrifices accuracy and reduces
unrealistic results. This paper proposes a hybrid analysis method that can
reduce analysis time. The idea is that a large speed-up would be possible by
removing those events that are repetitious and unnecessary for simulation.