TCAD Newsletter - September 2009 Issue
Placing you one click away from the best new CAD research!


Regular Issue Papers
====================

Variation-Aware Structural Synthesis of Analog Circuits via Hierarchical Building Blocks and Structural Homotopy
McConaghy, T.; Palmers, P.; Steyaert, M.; Gielen, G. G. E.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5208483&isnumber=5208458

This paper presents MOJITO-R, a tool that performs variation-aware structural
synthesis of analog circuits. It returns trustworthy topologies, by searching
across a space of thousands of possible topologies defined by
hierarchically-organized analog structural building blocks. "Structural
homotopy" conducts search at several objective-function tightening levels
(numbers of process corners) simultaneously. Multi-objective evolutionary
search returns sized topologies which trade off power, area, performances, and
yield.  


A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing Biochips
Yuh, P.-H.; Sapatnekar, S. S.; Yang, C.-L.; Chang, Y.-W.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5208480&isnumber=5208458

Due to recent advances in microfluidics technology, digital microfluidic
biochips and their associated CAD problems have gained much attention, most of
which has been devoted to direct-addressing biochips. This paper solves the
droplet routing problem under the more scalable cross-referencing biochip
paradigm. It proposes the first droplet routing algorithm that directly solves
the problem of routing. We first present an optimal basic integer linear
programming (ILP) formulation.  


Probabilistic Analysis and Design of Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits
Zhang, J.; Patil, N. P.; Mitra, S.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5208464&isnumber=5208458

Metallic Carbon Nanotubes (CNTs) pose a major barrier to the design of digital
logic circuits using Carbon Nanotube Field Effect Transistors (CNFETs).
Metallic CNTs create source to drain shorts in CNFETs resulting in undesirable
effects such as excessive leakage and degraded noise margins. No known CNT
growth technique guarantees 0% metallic CNTs. Therefore, special processing
techniques are required for removing metallic CNTs after CNT growth. This paper
presents a probabilistic model which incorporates processing and design
parameters, and enables quantitative analysis of the impact of metallic CNTs on
leakage, noise margin and delay variation of CNFET based digital logic
circuits.


Optimization of Data-Flow Computations Using Canonical TED Representation
Ciesielski, M.; Gomez-Prado, D.; Ren, Q.; Guillot, J.; Boutillon, E
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5208465&isnumber=5208458

An efficient graph-based method to optimize polynomial expressions in data-flow
computations is presented. The method is based on factorization, common
subexpression elimination and decomposition of algebraic expressions performed
on a canonical Taylor Expansion Diagram (TED) representation. It targets the
minimization of the latency and cost of arithmetic operators in the scheduled
implementation. The generated data flow graphs are better suited for high level
synthesis than those extracted directly from the initial specification or
obtained with traditional algebraic decomposition methods. 


Run-Time Adaptive Workload Estimation for Dynamic Voltage Scaling
Bang, S.-Y.; Bang, K.; Yoon, S.; Chung, E.-Y.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5208582&isnumber=5208458

Dynamic Voltage Scaling is an energy saving technique and its effectiveness
depends on the workload estimation accuracy. Several approaches tackle this
issue but still require profiling and poorly handle time-varying workloads. To
overcome these limitations, the authors propose a novel workload estimation
technique based on Kalman filter. We used both a cycle-accurate simulator and
an XScale board for MPEG clips for its validation. 


Efficient Power Network Analysis Considering Multidomain Clock Gating
Zhang, W.; Yu, W.; Hu, X.; Zhang, L.; Shi, R.; Peng, H.; Zhu, Z.; Chua-Eoan, L.; Murgai, R.; Shibuya, T.;
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5208485&isnumber=5208458

This paper proposes an efficient framework to analyze the worst case of voltage
variation of power network considering multi-domain clock gating. Firstly, a
frequency-domain based simulation method is proposed to obtain the time-domain
voltage response via vector fitting technique. Then, an algorithm is proposed
to find the worst-case voltage variation and corresponding clock gating
patterns. 


A-Stable and L-Stable High-Order Integration Methods for Solving Stiff Differential Equations
Gad, E.; Nakhla, M.; Achar, R.; Zhou, Y.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5208579&isnumber=5208458

This paper describes a new A-stable and L-stable integration method for
simulating the time-domain transient response of nonlinear circuits. The
proposed method, which is based on the Obreshkov formula, can be made of
arbitrary high-order while maintaining A-stability property. The new method
allows for adoption of higher-order integration methods for transient analysis
of electronic circuits while enabling them to take larger step sizes without
violating the stability, leading to faster simulations. 


Performance and Thermal-Aware Steiner Routing for 3-D Stacked ICs
Pathak, M.; Lim, S. K.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5208482&isnumber=5208458

This paper presents a performance and thermal-aware Steiner routing algorithm
for 3D stacked ICs. The algorithm consists of two steps: tree construction and
tree refinement. The tree construction algorithm builds a delay-oriented
Steiner tree under a given thermal profile. The 3D tree construction involves
minimization of two-variable Elmore delay function. In the tree refinement
algorithm, the through-silicon-vias (TSVs) are repositioned in existing Steiner
trees while preserving the original routing topology for further thermal
optimization. 


Real-Time Lossless Compression for Silicon Debug
Daoud, E. A.; Nicolici, N.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5208466&isnumber=5208458

To address the lack of observability for the internal circuit nodes during
silicon debug, embedded logic analysis enables real-time data acquisition from
a limited number of internal signals. This paper presents a novel architecture
for embedded logic analysis that enables real-time lossless compression of
debug data. A new compression ratio metric is proposed to capture the trade-off
between the area and the increase in the observation window. The proposed
architecture is particularly suitable for in-field debugging on application
boards, which have asynchronous events that inhibit the deterministic replay of
debug experiments.


ATPG-XP: Test Generation for Maximal Crosstalk-Induced Faults
Chun, S.; Kim, T.; Kang, S.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5208481&isnumber=5208458

This paper proposes a new test generation method for crosstalk-induced delay
faults, based on a conventional delay ATPG technique in order to consider
multiple aggressor crosstalk faults to maximize the noise of the victim line.
Since the proposed ATPG for crosstalk-induced delay faults uses physical and
timing information, it can reduce the search space of the backward implication
of the aggressor's constraints and it is helpful for reducing the ATPG time
cost. In addition, since the proposed technique uses traditional delay ATPG, it
can improve test effectiveness. 


Optimal Test Margin Computation for At-Speed Structural Test
Xiong, J.; Zolotov, V.; Visweswariah, C.; Habitz, P. A.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5208463&isnumber=5208458

At-speed test is necessary to detect subtle delay defects.  This procedure
tests chips at a slightly higher speed than the target frequency required in
the field.  The additional performance required on the tester is called test
margin. By taking advantage of statistical timing, this paper proposes an
optimal method of test margin determination to maximize yield while staying
within a prescribed Shipped Product Quality Loss limit. If process information
is available from wafer testing of scribe-line structures or on-chip process
monitoring circuitry, this information can be leveraged to determine a per-chip
test margin which can further improve yield.



Short Papers
============

Quadratic Backward Propagation of Variance for Nonlinear Statistical Circuit Modeling
Stevanovic, I.; McAndrew, C. C.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5208460&isnumber=5208458

Accurate statistical modeling and simulation are keys to ensure that integrated
circuits (ICs) meet specifications over the stochastic variations inherent in
IC manufacturing technologies. Backward propagation of variance (BPV) is a
general technique for statistical modeling of semiconductor devices. The BPV
approach assumes that statistical fluctuations are not large, so that
variations in device electrical performances can be modeled as linear functions
of process parameters. With technology scaling, device performance variability
over manufacturing variations becomes nonlinear. This paper extends the BPV
technique to take into account these nonlinearities. The theory behind the
technique is presented and applied to specific examples. 


Forward-Looking Reverse Order Fault Simulation for n-Detection Test Sets
Pomeranz, I.; Reddy, S. M.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5208459&isnumber=5208458

The concept of forward-looking reverse order fault simulation is extended to
n-detection test sets. Forward-looking reverse order fault simulation is an
efficient static test compaction process similar to reverse order fault
simulation, but with the advantage of producing test sets that do not contain
any unnecessary tests. Application of test compaction procedures to n-detection
test sets is important since the test sets are larger than conventional test
sets. It is demonstrated that forward-looking reverse order fault simulation
produces smaller test sets than reverse order fault simulation. The quality of
the resulting test sets is measured by their bridging fault coverage.