TCAD Newsletter - October 2009 Issue
Placing you one click away from the best new CAD research!


Keynote Paper
=============

Elastic Circuits
Carmona, J.; Cortadella, J.; Kishinevsky, M.; Taubin, A.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5247146&isnumber=5247118


Regular Issue Papers
====================

Simulation of Mutually Coupled Oscillators Using Nonlinear Phase Macromodels
Harutyunyan, D.; Rommes, J.; ter Maten, J.; Schilders, W.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5247126&isnumber=5247118         
Design of integrated RF circuits requires detailed insight in the behavior of
the used components. Unintended coupling and perturbation effects need to be
accounted for before production, but full simulation of these effects can be
expensive or infeasible. In this paper, we present a method to build nonlinear
phase macromodels of voltage-controlled oscillators. These models can be used
to accurately predict the behavior of individual and mutually coupled
oscillators under perturbation at a lower cost than full circuit simulations. 

Stable Reduced Models for Nonlinear Descriptor Systems Through Piecewise-Linear Approximation and Projection
Bond, B. N.; Daniel, L.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5247145&isnumber=5247118 
This paper presents theoretical and practical results concerning the stability
of piecewise-linear (PWL) reduced models for the purposes of analog
macromodeling. Results include proofs of input-output (I/O) stability for PWL
approximations to certain classes of nonlinear descriptor systems, along with
projection techniques which are guaranteed to preserve I/O stability in
reduced-order PWL models. The paper also derives a new PWL formulation and
introduces a new nonlinear projection, allowing to extend the stability results
to a broader class of nonlinear systems described by models containing
nonlinear descriptor functions. 

Closed-Form Delay and Crosstalk Models for RLC On-Chip Interconnects Using a Matrix Rational Approximation
Roy, S.; Dounavis, A.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5247152&isnumber=5247118

In this paper, a closed-form matrix rational-approximation algorithm is
proposed to efficiently model the delay and crosstalk noise of coupled on-chip
interconnects. A key feature of the proposed algorithm is that, for any
rational order, the approximation is obtained analytically in terms of
predetermined coefficients and the per-unit-length parameters. As a result, the
proposed method is not limited to fixed number of poles and provides a
mechanism to increase the accuracy for cases when inductive effects are
significant, the length of the line increases, or when the rise time of the
signal becomes sharper. An error criterion is provided to select the order of
approximation. 


HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection
Chakraborty, R. S.; Bhunia, S.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5247148&isnumber=5247118

Hardware intellectual-property (IP) cores have emerged as an integral part of
modern system-on-chip (SoC) designs. However, IP vendors are facing major
challenges to protect hardware IPs from IP piracy. This paper proposes a novel
design methodology for hardware IP protection using netlist-level obfuscation.
The proposed methodology can be integrated in the SoC design and manufacturing
flow to simultaneously obfuscate and authenticate the design. 


Utilizing Predictors for Efficient Thermal Management in Multiprocessor SoCs
Coskun, A. K.; Rosing, T. S.; Gross, K. C.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5247150&isnumber=5247118

Conventional thermal management techniques are reactive, as they take action
after temperature reaches a threshold. Such approaches do not always minimize
and balance the temperature, and they control temperature at a noticeable
performance cost. This paper investigates how to use predictors for forecasting
temperature and workload dynamics, and proposes proactive thermal management
techniques for multiprocessor system-on-chips. The predictors studied include
autoregressive moving average modeling and lookup tables. 


Electronic System-Level Synthesis Methodologies
Gerstlauer, A.; Haubelt, C.; Pimentel, A. D.; Stefanov, T. P.; Gajski, D. D.; Teich, J.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5247153&isnumber=5247118

With ever-increasing system complexities, all major semiconductor roadmaps have
identified the need for moving to higher levels of abstraction in order to
increase productivity in electronic system design. Most recently, many
approaches and tools that claim to realize and support a design process at the
so-called electronic system level (ESL) have emerged. However, faced with the
vast complexity challenges, in most cases at best, only partial solutions are
available. This paper develops and proposes a novel classification for ESL
synthesis tools, and presents six different academic approaches in this
context. 


Maximum-Utility Scheduling of Operation Modes With Probabilistic Task Execution Times Under Energy Constraints
Lee, W. Y.; Kim, H.; Lee, H.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5247147&isnumber=5247118

This paper proposes a novel scheduling scheme that determines the instant
operation modes of multiple tasks. The tasks have probabilistic execution times
and are executed on discrete operation modes providing different utilities with
different energy consumptions. The works first designs an optimal offline
scheduling scheme that stochastically maximizes the cumulative utility of the
tasks under energy constraints, at the cost of heavy computational overhead.
Next, the optimal offline scheme is modified to an approximate online
scheduling scheme. The online scheme has little runtime overhead and yields
almost the maximum utility, with an energy budget that is given at runtime. The
difference between the maximum utility and the output utility of the online
scheme is bounded by a controllable input value. 


Post-Silicon Bug Localization in Processors Using Instruction Footprint Recording and Analysis (IFRA)
Park, S.-B.; Hong, T.; Mitra, S.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5247122&isnumber=5247118

Instruction Footprint Recording and Analysis (IFRA) overcomes challenges
associated with an expensive step in post-silicon validation of
processors-pinpointing the bug location and the instruction sequence that
exposes the bug from a system failure. On-chip recorders collect instruction
footprints (information about flows of instructions and what the instructions
did as they passed through various design blocks) during the normal operation
of the processor in a post-silicon system validation setup. Upon system
failure, the recorded information is scanned out and analyzed offline for bug
localization. Special self-consistency-based program analysis techniques,
together with the test program binary of the application executed during
post-silicon validation, are used for this purpose. Major benefits of using
IFRA over traditional techniques for post-silicon bug localization are as
follows: 1) it does not require full system-level reproduction of bugs, and 2)
it does not require full system-level simulation. 


Fast and Accurate Prediction of the Steady-State Throughput of Multicore Processors Under Thermal Constraints
Rao, R.; Vrudhula, S.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5247119&isnumber=5247118

This paper describes a fast and accurate technique to predict the steady-state
throughput and the corresponding power consumption of a homogeneous multicore
processor for a given benchmark workload while accounting for speed reduction
due to thermal constraints. The expressions contain several parameters of
interest to a system designer, like the static and dynamic-power consumptions
(for hottest block and for full chip), the vertical thermal resistance of the
hottest block, the leakage sensitivity to temperature, the chip threshold
temperature, the ambient temperature, etc. Their computational complexity is
independent of the number of cores. These are incorporated in a system-level
multicore power/thermal simulator that uses the PTScalar power model and the
Hotspot thermal model. 


A Novel Faster-Than-at-Speed Transition-Delay Test Method Considering IR-Drop Effects
Ahmed, N.; Tehranipoor, M.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5247155&isnumber=5247118

Interconnect defects such as weak resistive opens, shorts, and bridges increase
the path delay affected by a pattern during manufacturing test but are not
significant enough to cause a failure at functional frequency. In this paper, a
new faster-than-at-speed method is presented for delay test pattern application
to screen small delay defects. Given a test pattern set, the technique groups
the patterns into multiple subsets with close path delay distribution and
determines an optimal test frequency considering both positive slack and
performance degradation due to IR-drop effects. Since, the technique does not
increase the test frequency to an extent that any paths exercised at the rated
functional frequency may fail, it avoids any scan flip-flop masking. 


High-Level Test Synthesis With Hierarchical Test Generation for Delay-Fault Testability
Wang, S.-J.; Yeh, T.-H.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5247154&isnumber=5247118

A high-level test synthesis (HLTS) method targeted for delay-fault testability
is presented in this paper. The proposed method, when combined with
hierarchical test-pattern generation for embedded modules, guarantees a 100%
delay test coverage for detectable faults in modules. A study on the delay
testability problem in behavior level shows that low delay-fault coverage is
usually attributed to the fact that a two-pattern test for delay testing cannot
be delivered to modules under test in two consecutive cycles. To solve the
problem, we propose an HLTS method that ensures that valid test pairs can be
sent to each module through synthesized circuit hierarchy. 


Automated Design Debugging With Abstraction and Refinement
Safarpour, S.; Veneris, A.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5247156&isnumber=5247118

Design debugging is one of the major remaining manual processes in the
semiconductor design cycle. Despite recent advances in the area of automated
design debugging, more effort is required to cope with the size and complexity
of today's designs. This paper introduces an abstraction and refinement
methodology to enable current debuggers to operate on designs that are orders
of magnitude larger than otherwise possible. Two abstraction techniques are
developed with the goals of improving debugger performance for different
circuit structures: State abstraction is aimed at reducing the problem size for
circuits consisting purely of primitive gates, while function abstraction
focuses on designs that also contain modular and hierarchical information. In
both methods, after an initial abstracted model is created, the problem can be
solved by an existing automated debugger. If an error site is abstracted,
refinement is necessary to reintroduce some of the abstracted components back
into the design.