TCAD Newsletter - November 2009 Issue
Placing you one click away from the best new CAD research!


Regular Papers
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A Methodology to Predict the Impact of Substrate Noise in Analog/RF Systems
Bronckers, S.; Scheir, K.; Van der Plas, G.; Vandersteen, G.; Rolain, Y.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5290343&isnumber=5290339

Substrate noise problems in a System-On-a-Chip (SoC) hamper the smooth
co-habitation between the analog and digital circuitry on the same die. Solving
those problems will shorten the time-to-market. This paper presents a
methodology that gives the designer the necessary insight to solve this
substrate noise problem. The methodology combines the strengths of the EM
simulator, the parasitic extractor and the circuit simulator. Its main assets
are the ease-of-use, an acceptable simulation time and a good accuracy.
Moreover this methodology does not need doping profiles that are hard to get
hold off.


Globally Reliable Variation-Aware Sizing of Analog Integrated Circuits via Response Surfaces and Structural Homotopy
McConaghy, T.; Gielen, G. G. E.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5290344&isnumber=5290339

This paper presents SANGRIA, a tool for automated globally reliable
variation-aware sizing of analog integrated circuits. Its keys to efficient
search are adaptive response surface modeling, and a new concept, structural
homotopy. Structural homotopy embeds homotopy-style objective function
tightening into the search state's structure, not dynamics. Searches at several
different levels are conducted simultaneously: The loosest level does nominal
dc simulation, and tighter levels add more analyses and process, environmental
corners. New randomly generated designs are continually fed into the lowest
(cheapest) level, always trying new regions to avoid premature convergence. 


Incremental Large-Scale Electrostatic Analysis
Ye, Z.; Zhu, Z.; Phillips, J. R.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5290348&isnumber=5290339

This paper presents methods to accelerate the solution of multiple related
linear systems of equations. Such systems arise, for example, in building
pattern libraries for interconnect parasitic extraction, parasitic extraction
under process variation, and parameterized interconnect characterization.  The
proposed techniques include methods based on a generalized form of "recycled"
Krylov subspace methods that use sharing of information between related systems
of equations to accelerate the iterative solution and methods to reuse
computational effort during system matrix setup.  


Robust Simulation Methodology for Surface-Roughness Loss in Interconnect and Package Modelings
Chen, Q.; Choi, H. W.; Wong, N.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5290342&isnumber=5290339

In multi-GHz integrated circuit (IC) design, the extra energy loss caused by
conductor surface roughness in metallic interconnects and packagings is more
evident than ever before and demands explicit consideration for accurate
prediction of signal integrity and energy consumption. Existing techniques
based on analytical approximation, despite simple formulations, suffer from
restrictive valid ranges, namely, either for small or large
roughness/frequencies. This paper proposes a robust and efficient numerical
simulation methodology applicable to evaluating general surface roughness,
described by parameterized stochastic processes, across a wide frequency band.

PaRS: Parallel and Near-Optimal Grid-Based Cell Sizing for Library-Based Design
Wu, T.-H.; Davoodi, A.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5290357&isnumber=5290339

This paper proposes PaRS, a parallel and randomized algorithm and tool to solve
the cell sizing problem on a grid. PaRS is formulated based on an optimization
framework known as Nested Partitions. PaRS uses parallelism from a novel
perspective to better identify the optimization direction. It achieves
near-optimal solutions. The parallel nature of PaRS makes it highly scalable. 


BSG-Route: A Length-Constrained Routing Scheme for General Planar Topology
Yan, T.; Wong, M. D. F.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5290341&isnumber=5290339

Previous length-constrained routers all have assumptions on the routing
topology. This article presents the first routing scheme that is free of any
restriction on the routing topology. Moreover, its gridless feature makes the
performance independent of the input routing grid size. The novelty of this
work is that the length-constrained routing problem is regarded as an area
assignment problem, which is then transformed into a mathematical programming
problem by the use of a placement structure, Bounded-Sliceline Grid (BSG). 


A Feedback-Based Approach to DVFS in Data-Flow Applications
Alimonda, A.; Carta, S.; Acquaviva, A.; Pisano, A.; Benini, L.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5290359&isnumber=5290339

In this work the authors present a control-theoretic approach to Dynamic
Voltage/Frequency Scaling (DVFS) for data-flow models of computations mapped to
Multiprocessor Systems on Chip (MPSoC) architectures. They discuss, in
particular, non linear control approaches to deal with general streaming
applications containing both pipeline and parallel stages. 


An Optimal Solution for the Heterogeneous Multiprocessor Single-Level Voltage-Setup Problem
Chu, E. T.-H.; Huang, T.-Y.; Tsai, Y.-C.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5290350&isnumber=5290339

A heterogeneous multi-processor (HeMP) system consists of heterogeneous
processors. A low-power real-time scheduling algorithm is required to minimize
energy consumption and meet deadlines. Existing works assume that processor
speeds are known as a priori and cannot deliver the optimal energy-saving. The
problem of determining the optimal voltage for each processor to minimize
energy consumption is called the voltage setup problem. This is the first work
to propose the optimal solution for the HeMP single-level voltage setup problem
proved to be NP-hard. 


A Software-Only Solution to Use Scratch Pads for Stack Data
Shrivastava, A.; Kannan, A.; Lee, J.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5290354&isnumber=5290339

A dynamic scratch pad memory (SPM) management scheme for program stack data
with the objective of processor power reduction is presented. Basic technique
does not need the SPM size at compile time, does not mandate any hardware
changes, does not need profile information, and seamlessly integrates support
for recursive functions. Stack frames are managed using a software SPM manager,
integrated into the application binary.


A Statistical Diagnosis Approach for Analyzing Design-Silicon Timing Mismatch
Callegari, N.; Bastani, P.; Wang, L.-C.; Abadir, M. S.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5290347&isnumber=5290339

Explaining mismatch between predicted timing behavior from modeling and
simulation, and the observed timing behavior measured on silicon chips can be
challenging.  This paper proposes using a statistical learning method called
Support Vector analysis to statistically analyze all known sources of
uncertainty with the goal to rank which sources contribute the most to the
observed mismatch. 


Low-Power Scan Operation in Test Compression Environment
Czysz, D.; Kassab, M.; Lin, X.; Mrugalski, G.; Rajski, J.; Tyszer, J.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5290349&isnumber=5290339

This paper presents a new and comprehensive low-power test scheme compatible
with a test compression environment. The key contribution of this paper is a
flexible test-application framework that achieves significant reductions in
switching activity during all phases of scan test: loading, capture, and
unloading. In particular, we introduce a new on-chip continuous-flow
decompressor. Its synergistic use with a power-aware scan controller allows a
significant reduction of toggling rates when feeding scan chains with
decompressed test patterns. 


QC-Fill: Quick-and-Cool X-Filling for Multicasting-Based Scan Test
Tzeng, C.-W.; Huang, S.-Y.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5290353&isnumber=5290339

This paper presents an X-fill scheme that properly utilizes the don't-care bits
in test patterns to simultaneously reduce the test time as well as the test
power. This scheme, called Quick-and-Cool X-fill (QC-Fill), built upon the
multicasting-based scan architecture, further leverages on the merits of
previous low-capture-power X-fill methods through techniques like
multicasting-driven X-fill and clique stripping. QC-Fill is independent of the
automatic test pattern generation patterns and does not require any extra area
overhead. 


Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment
Wu, M.-F.; Huang, J.-L.; Wen, X.; Miyase, K.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5290346&isnumber=5290339

Yield loss caused by excessive power supply noise has become a serious problem
in at-speed scan testing. Although X-filling techniques are available to reduce
the launch cycle switching activity, their performance may not be satisfactory
in the linear-decompressor-based test compression environment. This paper
solves this problem by proposing a novel integrated automatic test pattern
generation scheme that efficiently and performs compressible low-capture-power
X-filling. Related theoretical principles are established, based on which the
problem size is substantially reduced. The proposed scheme is validated by
benchmark circuits, as well as an industry design in the embedded deterministic
test environment.


Short Papers
============

Efficient Additive Statistical Leakage Estimation
Cheng, L.; Gupta, P.; He, L.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5290345&isnumber=5290339

Nominal power estimation is quick, but gives minimal information. Statistical
power analysis can provide information on yield, chip robustness, etc., but
current methods are unnecessarily slow and complex. This is primarily because
the existing leakage power models are not directly additive. Hence the
covariances between each pair of circuit elements need to be recalculated,
which is not efficient. This paper proposes a simple additive polynomial
leakage variation model. With additivity, the chip leakage power can be
calculated.