TCAD Newsletter - December 2009 Issue Placing you one click away from the best new CAD research! Special Section =============== Special Section on the IEEE Symposium on Application Specific Processors 2008 Orailoglu, A.; Pozzi, L. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5324040&isnumber=5324016 Design-Space Exploration of Resource-Sharing Solutions for Custom Instruction Set Extensions Zuluaga, M.; Topham, N. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5324027&isnumber=5324016 Resource sharing during synthesis of Instruction Set Extensions (ISEs) can reduce the die area and energy consumption of a customized processor. However, coupling multiple nodes among the ISEs, if performed naively, can increase their latency considerably. The authors show in this paper that an appropriate level of resource sharing provides a significantly simpler design with only modest increase in average latency for extension instructions. Their main contribution is the introduction of a parametric method for exploring the trade-offs that can be achieved between instruction latency and implementation complexity. TRaX: A Multicore Hardware Architecture for Real-Time Ray Tracing Spjut, J.; Kensler, A.; Kopta, D.; Brunvand, E. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5324031&isnumber=5324016 TRaX is a highly parallel multi-threaded, multicore processor architecture designed for real-time ray tracing. In this paper the authors describe the TRaX architecture and the performance results are compared to other architectures used for ray tracing. Simulated results indicate that a multicore version of the TRaX architecture running at a modest speed of 500MHz provides real-time ray traced images for scenes of a complexity found in video games. ReSPIR: A Response Surface-Based Pareto Iterative Refinement for Application-Specific Design Space Exploration Palermo, G.; Silvano, C.; Zaccaria, V. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5324029&isnumber=5324016 In this paper, an efficient DSE methodology for application-specific MPSoC is proposed. The methodology is capable of finding a set of good candidate architecture configurations by minimizing simulations to be executed. The methodology combines Design of Experiments and Response Surface Modeling techniques for managing constraints. First, the DoE phase generates an initial plan of experiments used to create a coarse view of the target design space to be explored by simulations. Then, a set of RSM techniques is used to refine the simulation-based exploration by exploiting application-specific constraints to identify the maximum number of feasible solutions. Multicore Architectures With Dynamically Reconfigurable Array Processors for Wireless Broadband Technologies Han, W.; Yi, Y.; Muir, M.; Nousias, I.; Arslan, T.; Erdogan, A. T. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5324020&isnumber=5324016 This paper presents several new multi-core architectures for the WiMAX application based on coarse-grained dynamically reconfigurable processor cores. A simulation platform is proposed in order to explore and implement various multi-core solutions combining different memory architectures and task partitioning schemes. The paper describes the different architectures, the simulation environment and several task partitioning methods. Regular Papers ============== High-Level Synthesis Algorithm for the Design of Reconfigurable Constant Multiplier Chen, J.; Chang, C.-H. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5324042&isnumber=5324016 This paper presents a new high level design methodology for Reconfigurable Constant Multiplier. Common subexpressions in the preset constants are first eliminated to obtain a minimum depth directed acyclic graph (DAG). The DAG is converted into a primitive data flow graph. By scheduling each mobile adder into a control step within its legitimate time window with the minimum opportunity cost, mutually exclusive adders can be merged with significantly reduced adder and multiplexing cost. The opportunity cost for each scheduling decision is assessed by the probability displacement and disparity measures of the scheduled node as well as its predecessors and successors. ReSP: A Nonintrusive Transaction-Level Reflective MPSoC Simulation Platform for Design Space Exploration Beltrame, G.; Fossati, L.; Sciuto, D. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5324034&isnumber=5324016 This paper presents ReSP (Reflective Simulation Platform), a Transaction Level multi-processor simulation platform based on SystemC and Python. ReSP exploits the concept of reflection enabling the integration of SystemC components without source code modifications, and providing full observability of their internal state. ReSP offers fine-grained simulation control and supports the evaluation of different hardware/software configurations of a given application, allowing complete design space exploration. ReSP allows the evaluation of real-time applications by providing a transparent emulation of POSIX-compliant Real Time Operating Systems (RTOS) primitives. Thermal Balancing Policy for Multiprocessor Stream Computing Platforms Mulas, F.; Atienza, D.; Acquaviva, A.; Carta, S.; Benini, L.; De Micheli, G. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5324045&isnumber=5324016 Die-temperature control to avoid hotspots is critical in Multiprocessor System-on-Chip (MPSoCs) for stream computing. Since stream computing requires strict quality of service and timing constraints, the real-time performance impact of thermal balancing policies must be carefully evaluated. In this paper the authors present a lightweight thermal balancing policy, MiGra, which bounds on-chip temperature gradients via task migration. This policy exploits run-time temperature and workload information of streaming applications to define run-time thermal migration patterns that minimize deadline misses. Threshold Testing: Improving Yield for Nanoscale VLSI Jiang, Z.; Gupta, S. K. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5324024&isnumber=5324016 Recently, the authors have proposed the notion of error tolerance to improve yield for a wide range of high-performance digital applications. In this paper, they propose a new testing approach called threshold testing to practically exploit the notion of error tolerance for applications where errors with absolute numerical magnitudes lower than an application-specified threshold are acceptable. They propose a new automatic test pattern generator (ATPG) for threshold testing for single stuck-at faults.