April 2013 Newsletter 
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SPECIAL SECTION ON THREE-DIMENSIONAL (3-D) INTEGRATED CIRCUITS

Xie, Y. ; Loh, G.
Guest Editorial
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6480867

SPECIAL SECTION PAPERS

Yao, W. ; Pan, S. ; Achkir, B. ; Fan, J. ; He, L.
Modeling and Application of Multi-Port TSV Networks in 3-D IC
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6480846

Through-silicon-via (TSV) enables vertical connectivity between stacked chips
or interposer and is a key technology for 3-D integrated circuits (ICs). While
arrays of TSVs are needed in 3-D IC, there only exists a frequency- dependent
resistance, inductance, conductance and capacitance circuit model for a pair of
TSVs with coupling between them. In this paper, we develop a simple yet
accurate circuit model for a multiport TSV network (e.g., coupled TSV array) by
decomposing the network into a number of TSV pairs and then applying circuit
models for each of them. We call the new model a pair-based model for the
multiport TSV network. It is first verified against a commercial
electromagnetic solver for up to 20 GHz and subsequently employed for a variety
of examples for signal and power integrity analysis.

Hsu, M.-K. ; Balabanov, V. ; Chang, Y.-W.
TSV-Aware Analytical Placement for 3-D IC Designs Based on a Novel
Weighted-Average Wirelength Model
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6480847

Through-silicon vias (TSVs) are required for transmitting signals among
different dies for the 3-D integrated circuit (IC) technology. The significant
silicon areas occupied by TSVs bring critical challenges for 3-D IC placement.
Unlike most published 3-D placement works that only minimize the number of TSVs
during placement due to the limitations in their techniques, this paper
proposes a new 3-D cell placement algorithm that can additionally consider the
sizes of TSVs and the physical positions for TSV insertion during placement.
The algorithm consists of three stages: 1) 3-D analytical global placement with
density optimization and whitespace reservation for TSVs; 2) TSV insertion and
TSV-aware legalization; and 3) layer-by-layer detailed placement. In
particular, the global placement is based on a novel weighted-average (WA)
wirelength model, giving the first published model that can outperform the
well-known log-sum-exp wirelength model theoretically and empirically. Also, a
scheme is proposed to enhance the numerical stability of the WA wirelength
model. Furthermore, 3-D routing can easily be accomplished by traditional 2-D
routers since the physical positions of TSVs are determined during placement.
Experimental results show the effectiveness of our algorithm. Compared with
state-of-the-art 3-D cell placement works, our algorithm can achieve the best
routed wirelength, TSV counts, and total silicon area, in shortest running
time.

Luo, G. ; Shi, Y. ; Cong, J.
An Analytical Placement Framework for 3-D ICs and Its Extension on Thermal
Awareness
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6480862

In this paper, we present a high-quality analytical 3-D placement framework. We
propose using a Huber-based local smoothing technique to work with a
Helmholtz-based global smoothing technique to handle the nonoverlapping
constraints. The experimental results show that this analytical approach is
effective for achieving tradeoffs between the wirelength and the
through-silicon-via (TSV) number. Compared to the state-of-the-art 3-D placer
ntuplace3d, our placer achieves more than 20% wirelength reduction, on average,
with a similar number of TSVs. Furthermore, we extend this analytical 3-D
placement framework with thermal awareness. While 2-D thermal-aware placement
simply follows uniform power distribution to minimize temperature, we show that
the same criterion does not work for 3-D ICs. Instead, we are able to prove
that when the TSV area in each bin is proportional to the lumped power
consumption of that bin and the bins in all tiers directly above it, the peak
temperature is minimized. Based on this criterion, we implement thermal
awareness in our analytical 3-D placement framework. Compared with a TSV
oblivious method, which only results in an 8% peak temperature reduction, our
method reduces the peak temperature by 34%, on average, with slightly less
wirelength overhead. These results suggest that considering the thermal effects
of TSVs is necessary and effective during the placement stage.

Sabry, M.M. ; Sridhar, A. ; Meng, J. ; Coskun, A.K. ; Atienza, D.
GreenCool: An Energy-Efficient Liquid Cooling Design Technique for 3-D MPSoCs
Via Channel Width Modulation
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6480864

Liquid cooling using interlayer microchannels has appeared as a viable and
scalable packaging technology for 3-D multiprocessor system-on-chips (MPSoCs).
Microchannel-based liquid cooling, however, can substantially increase the
on-chip thermal gradients, which are undesirable for reliability, performance,
and cooling efficiency. In this paper, we present GreenCool, an optimal design
methodology for liquid-cooled 3-D MPSoCs. GreenCool simultaneously minimizes
the cooling energy for a given system while maintaining thermal gradients and
peak temperatures under safe limits. This is accomplished by tuning the heat
transfer characteristics of the microchannels using channel width modulation.
Channel width modulation is compatible with the current process technologies
and incurs minimal additional fabrication costs. Through an extensive set of
experiments, we show that channel width modulation is capable of complementing
and enhancing the benefits of temperature-aware floorplanning. We also
experiment with a 16-core 3-D system with stacked dynamic random-access memory,
for which GreenCool improves energy efficiency by up to 53% with respect to no
channel modulation.

Kandalaft, N. ; Rashidzadeh, R. ; Ahmadi, M.
Testing 3-D IC Through-Silicon-Vias (TSVs) by Direct Probing
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6480855

Testing the integrity of interconnects realized by through silicon vias (TSVs)
in 3-D integrated circuits (3-D IC) is considered a challenging task. TSVs are
excessively small and fragile for current probe technology. In this paper, a
new spring-type probe using microelectromechanical systems (MEMS) technology is
presented. The implemented MEMS probe supports the required pitch for TSV
direct probing and minimizes the undesired scrub marks on TSV surface.
Simulation results indicate that the implemented MEMS probe can operate at the
gigahertz frequency range without significant test signal degradation.

Noia, B. ; Chakrabarty, K.
Pre-Bond Probing of Through-Silicon Vias in 3-D Stacked ICs
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6480863

Through-silicon via (TSV)-based 3-D stacked ICs are becoming increasingly
important in the semiconductor industry, yet pre-bond testing of TSVs continues
to be difficult with current technologies. In this paper, we present a test and
discrete Fourier transform method for pre-bond testing of TSVs using probe
technology. We describe the on-die test architecture and probe technique needed
for TSV testing, in which individual probe needles make contact with multiple
TSVs at a time. We also describe methods for capacitance and resistance
measurements, as well as stuck-at and leakage tests. Simulation results using
HSPICE are presented for a TSV network. We demonstrate that we can achieve high
resolution in these measurements, and therefore high accuracy in defect
detection when we target one or multiple TSVs at a time. We also show that the
test outcome is reliable even in the presence of process variations or multiple
defective TSVs.

Jiang, L. ; Xu, Q. ; Eklow, B.
On Effective Through-Silicon Via Repair for 3-D-Stacked ICs
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6480868

3-D-stacked integrated circuits (ICs) that employ through-silicon vias (TSVs)
to connect multiple dies vertically have gained wide-spread interest in the
semiconductor industry. In order to be commercially viable, the assembly yield
for 3-D-stacked ICs must be as high as possible, requiring TSVs to be
reparable. Existing techniques typically assume TSV faults to be uniformly
distributed and use neighboring TSVs to repair faulty ones, if any. In
practice, however, clustered TSV faults are quite common due to the fact that
the TSV bonding quality depends on surface roughness and cleanness of silicon
dies, rendering prior TSV redundancy solutions less effective. Furthermore,
existing techniques consume a lot of redundant TSVs that are still costly in
the current TSV process. This inefficient TSV redundancy can limit the amount
of TSVs that is allowed to use and may even become the obstacle to commercial
production. To resolve this problem, we present a novel TSV repair framework,
including a hardware redundancy architecture that enables faulty TSVs to be
repaired by redundant TSVs that are farther apart, the corresponding repair
algorithm and the redundancy architecture construction. By doing so, the
manufacturing yield for 3-D-stacked ICs can be dramatically improved, as
demonstrated in our experimental results.

Chou, C.-W. ; Huang, Y.-J. ; Li, J.-F.
A Built-In Self-Repair Scheme for 3-D RAMs With Interdie Redundancy
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6480861

3-D integration using through silicon via is an emerging technology for
integrated circuit designs. Random access memory (RAM) is one good candidate
for the application of 3-D integration technology. However, yield will be a key
challenge for the volume production of 3-D RAMs. In this paper, we present
yield-enhancement techniques for 3-D RAMs. An interdie redundancy scheme is
proposed to improve the yield of 3-D RAMs. Three stacking flows with respect to
different bonding technologies for 3-D RAMs with interdie redundancy are
proposed as well.  Finally, a built-in self-repair (BISR) scheme is proposed to
perform the repair of 3-D RAMs with interdie redundancies. The BISR circuits in
two stacked dies can work together to allocate interdie redundancies.
Simulation results show that the proposed yield-enhancement techniques can
effectively improve the yield of 3-D RAMs.

Ye, Y. ; Xu, J. ; Huang, B. ; Wu, X. ; Zhang, W. ; Wang, X. ; Nikdast, M. ;
Wang, Z. ; Liu, W. ; Wang, Z.
3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6480869

Optical networks-on-chip (ONoCs) are emerging communication architectures that
can potentially offer ultrahigh communication bandwidth and low latency to
multiprocessor systems-on-chip (MPSoCs). In addition to ONoC architectures, 3-D
integrated technologies offer an opportunity to continue performance
improvements with higher integration densities. In this paper, we present a 3-D
mesh-based ONoC for MPSoCs, and new low-cost nonblocking 4x4, 5x5, 6x6, and 7x7
optical routers for dimension-order routing in the 3-D mesh-based ONoC.
Besides, we propose an optimized floorplan for the 3-D mesh-based ONoC. The
floorplan follows the regular 3-D mesh topology but implements all optical
routers in a single optical layer. The floorplan is optimized to minimize the
number of extra waveguide crossings caused when merging the 3-D ONoC to one
optical layer. Based on a set of real applications and uniform traffic pattern,
we develop a SystemC-based cycle-accurate NoC simulator and compare the 3-D
mesh-based ONoC with the matched 2-D mesh-based ONoC and 2-D electronic NoC for
performance and energy efficiency. Additionally, we quantitatively analyze
thermal effects on the 3-D 8x8x2 mesh-based ONoC.

Weis, C. ; Loi, I. ; Benini, L. ; Wehn, N.
Exploration and Optimization of 3-D Integrated DRAM Subsystems
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6480866

Energy efficiency is the major optimization criterion for systems-on-chip
(SoCs) for mobile devices (smartphones and tablets). Through silicon via (TSV)
technology enables 3-D integration of dies and the heterogeneous stacking of
multiple memory or logic layers, allowing increased bandwidth and lower energy
consumption of the memory interface compared to traditional approaches. In this
paper, we explore the 3-D-DRAM architecture design space.  The result is an
optimized 2 Gb 3-D-DRAM, which shows a 83% lower energy/bit than a 2 Gb
LPDDR2x32 device.  Furthermore, we propose a highly energy-efficient DRAM
subsystem for next-generation 3-D-integrated SoCs, consisting of a SDR/DDR
3-D-DRAM controller and an attached 3-D-DRAM cube with fine-grained access and
a flexible (WIDE-IO) interface. We assess the energy efficiency using a
synthesizable model of the SDR/DDR 3-D- DRAM channel controller (CC) as well as
functional models of the 3-D-stacked DRAM, including an accurate power
estimation engine. We also investigate different DRAM families (WIDE IO
SDR/DDR, LPDDR, and LPDDR2) and densities from 256 Mb to 4 Gb per channel. The
implementation results of the proposed 3-D-DRAM subsystem show that energy
optimized accesses to the 3-D-DRAM enable up to 50% energy savings compared to
standard accesses. To the best of our knowledge this is the first design space
exploration for 3-D-stacked DRAM considering different technologies based on
real-world physical data and the first design of a 3-D-DRAM CC and 3- D-DRAM
model featuring co-optimization of memory and controller architecture.


SPECIAL SECTION SHORT PAPER

Valamehr, J. ; Sherwood, T. ; Kastner, R. ; Marangoni-Simonsen, D. ; Huffmire,
T. ; Irvine, C. ; Levin, T.
A 3-D Split Manufacturing Approach to Trustworthy System Development
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6480852

Securing the supply chain of integrated circuits is of utmost importance to
computer security. In addition to counterfeit microelectronics, the theft or
malicious modification of designs in the foundry can result in catastrophic
damage to critical systems and large projects. In this letter, we describe a
3-D architecture that splits a design into two separate tiers: one tier that
contains critical security functions is manufactured in a trusted foundry;
another tier is manufactured in an unsecured foundry. We argue that a split
manufacturing approach to hardware trust based on 3-D integration is viable and
provides several advantages over other approaches.

REGULAR PAPERS

ANALOG, MIXED-SIGNAL, AND RF CIRCUITS

Ferent, C. ; Doboli, A.
Symbolic Matching and Constraint Generation for Systematic Comparison of Analog
Circuits
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6480851

This paper proposes an automated technique for systematically generating
comparison data between two analog circuits. The comparison data presents the
similar and distinguishing performance characteristics of the circuits with
respect to DC-gain, bandwidth, common-mode rejection ratio, noise, and
sensitivity. The comparison data is important for getting insight into the
common and unique benefits of a circuit, selecting fitting circuit topologies
for system design, and refining and optimizing circuit topologies. The
technique utilizes matching of the topologies and symbolic expressions of the
compared circuits to find the nodes with similar electric behavior. The impact
on performance of the unmatched nodes is used to express the differentiating
characteristics of the circuits.  Experiments illustrate the technique for a
pair of analog circuit designs.

MODELING AND SIMULATION

Zhuo, C. ; Sylvester, D. ; Blaauw, D.
A Statistical Framework for Post-Fabrication Oxide Breakdown Reliability
Prediction and Management
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6480870

Oxide breakdown has become an increasingly pressing reliability issue in modern
very large scale integration design with ultrathin oxides. The conventional
guard-band methodology assumes uniformly thin oxide thickness, resulting in
overly pessimistic reliability estimation that severely degrades system
performance. In this paper, we present the use of limited post-fabrication
measurements of oxide thicknesses from on-chip sensors to aid in the chip-level
oxide breakdown reliability management. A key challenge, which is the focus of
this paper, is precisely predicting and managing the reliability condition of
each chip with a limited number of measurements and quantifying the tradeoff
between reliability margin and system performance. Given the post-fabrication
measurements, chip oxide breakdown reliability can be formulated as a
conditional distribution that allows one to achieve a significantly more
accurate chip lifetime estimation. The estimation is then used to individually
tune the supply voltage of each chip for performance maximization while
maintaining or improving the reliability. Experimental results show that, by
using 25 measurements, the proposed method can achieve an average of 19%
performance improvement, and a 27% maximum for a design with up to 50 million
devices, with an average operation time of approximately 0.4 s per chip.

TEST

Huang, Y.-C. ; Tsai, M.-H. ; Ding, W.-S. ; Li, J.C.-M. ; Chang, M.-T. ; Tsai,
M.-H. ; Tseng, C.-M. ; Li, H.-C.
Test Clock Domain Optimization to Avoid Scan Shift Failure Due to Flip-Flop
Simultaneous Triggering
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6481611

This paper presents a design for testability technique to avoid scan shift
failure due to flipÐflop simultaneous triggering. The proposed technique
changes test clock domains of flipÐflops in the regions where severe IR-drop
problems occur. A massive parallel algorithm using a graphic processor unit is
adopted to speed up the IR-drop simulation during optimization. The
experimental data on large benchmark circuits show that peak IR-drop values are
reduced by 15% on average compared with the circuit after simple MD-SCAN
partition. Our proposed technique quickly optimizes a half-million-gate design
within two hours.