September 2013 Newsletter Placing you one click away from the best new CAD research! Plain-text version at http://www.umn.edu/~tcad/newsletter/2013-09.txt REGULAR PAPERS EMBEDDED SYSTEMS Acquaviva, A. ; Bombieri, N. ; Fummi, F. ; Vinco, S. Semi-Automatic Generation of Device Drivers for Rapid Embedded Platform Development http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6582616 IP core integration into an embedded platform implies the implementation of a customized device driver complying with both the IP communication protocol and the CPU organization (single processor, SMP, AMP). Such a close dependence between driver and platform organization makes reuse of already existing device drivers very hard. Designers are forced to manually customize the driver code to any different organization of the target platform. This results in a very time-consuming and error-prone task. In this paper, we propose a methodology to semi- automatically generate customized device drivers, thus allowing a more rapid embedded platform development. The methodology exploits the testbench provided with the RTL IP module for extracting the formal model of the IP communication protocol. Then, a taxonomy of device drivers based on the CPU organization allows the system to determine the characteristics of the target platform and to obtain a template of the device driver code. This requires some manual support to identify the target architecture and to generate the desired device driver functionality. The template is used then to automatically generate drivers compliant with 1) the CPU organization, 2) the use in a simulated or in a real platform, 3) the interrupt support, 4) the operating system, 5) the I/O architecture, and 6) possible parallel execution. The proposed methodology has been successfully tested on a family of embedded platforms with different CPU organizations. EMERGING TECHNOLOGIES Luo, Y. ; Chakrabarty, K. Design of Pin-Constrained General-Purpose Digital Microfluidic Biochips http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6582577 Digital microfluidic biochips are being increasingly used for biotechnology applications. The number of control pins used to drive electrodes is a major contributor to the fabrication cost for disposable biochips in a highly cost- sensitive market. Most prior work on pin-constrained biochip design determines the mapping of a small number of control pins to a larger number of electrodes according to the specific schedule of fluid-handling operations and routing paths of droplets. Such designs are, therefore, specific to the bioassay application, hence sacrificing some of the flexibility associated with digital microfluidics. We propose a design method to generate an application- independent pin-assignment configuration with a minimum number of control pins. Layouts of commercial biochips and laboratory prototypes are used as case studies to evaluate the proposed design method for determining a suitable pin-assignment configuration. Compared with previous pin-assignment algorithms, the proposed method can reduce the number of control pins and facilitate the general-purpose use of digital microfluidic biochips for a wider range of applications. MODELING AND SIMULATION Lai, S. ; Yan, B. ; Li, P. Localized Stability Checking and Design of IC Power Delivery With Distributed Voltage Regulators http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6582611 Placing multiple voltage regulators onto the die is an effective way of enabling distributed on-chip voltage regulation and provides significant benefits in suppressing various types of power supply noise. However, the complex interactions between the active voltage regulators and the large passive subnetwork may render the complete power delivery network (PDN) unstable, leading to design failures. While traditional stability measures such as phase margin are not applicable to regulated PDNs that have a large number of loops, a brute-force analysis of network stability can be impractical due to the high complexity of a given PDN. We present a hybrid stability margin concept and the associated stability-checking method for PDNs with integrated linear low-dropout voltage regulators (LDOs). With theoretical rigor, the proposed approach is local in the sense that the stability of the entire network can be efficiently examined through a hybrid stability constraint that is defined locally for individual LDOs. In the same spirit, we propose a localized LDO design methodology that optimizes individual LDOs in a stand-alone manner while ensuring the network-level stability. Key circuit-level design considerations and tradeoffs involved in stability-ensuring LDO design are also discussed. PHYSICAL DESIGN Chen, Y. ; Kursun, E. ; Motschman, D. ; Johnson, C. ; Xie, Y. Through Silicon Via Aware Design Planning for Thermally Efficient 3-D Integrated Circuits http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6582598 3-D integrated circuits (3-D ICs) offer performance advantages due to their increased bandwidth and reduced wire- length enabled by through-silicon-via structures (TSVs). Traditionally TSVs have been considered to improve the thermal conductivity in the vertical direction. However, the lateral thermal blockage effect becomes increasingly important for TSV via farms (a cluster of TSV vias used for signal bus connections between layers) because the TSV size and pitch continue to scale in micrometer range and the metal to insulator ratio becomes smaller. Consequently, dense TSV farms can create lateral thermal blockages in thinned silicon substrate and exacerbate the local hotspots. In this paper, we propose a thermal-aware via farm placement technique for 3-D ICs to minimize lateral heat blockages caused by dense signal bus TSV structures. By incorporating thermal conductivity profile of via farm blocks in the design flow and enabling placement/aspect ratio optimization, the corresponding hotspots can be minimized within the wire-length and area constraints. Ho, Y.-K. ; Lee, H.-C. ; Chang, Y.-W. Escape Routing for Staggered-Pin-Array PCBs http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6582597 To accommodate the ever-growing pin number of complex printed circuit board (PCB) designs, the staggered pin array is introduced for modern designs with higher pin density. However, the escape routing for staggered pin arrays, which is a key component of PCB routing, is significantly different from that for grid arrays. This paper presents a routing algorithm for the escape routing for staggered-pin-array PCBs. We first analyze the properties of staggered pin arrays, and propose an orthogonal-side wiring style that fully utilizes the routing resource of the staggered pin array. A linear programming/integer linear programming-based algorithm is presented to solve the staggered-pin-array escape routing problem. Experimental results show that our approach successfully routes all test cases efficiently and effectively. Qiu, X. ; Marek-Sadowska, M. Routing Challenges for Designs With Super High Pin Density http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6582609 Footprint scaling may reduce wire lengths when more metal layers are available for routing. To achieve optimal wire length, footprint should be very small in which case pin density will be extremely high. However, high pin density may lead to detailed routing failure. We demonstrate that there is a threshold pin density beyond which standard routing heuristics fail to access pins on the bottom layer, even with unlimited number of metal layers available for routing. Future technologies, such as vertical slit field-effect transistor (VeSFET), may have layouts with pin density exceeding the threshold. We show that VeSFET layouts are still routable within footprint using two-sided routing. Compared to one-sided routing, two-sided routing achieves shorter wire lengths and fewer vias, hence lower interconnect capacitance and better performance. TEST Tenentes, V. ; Kavousianos, X. High-Quality Statistical Test Compression With Narrow ATE Interface http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6582565 In this paper, we present a novel compression method and a low-cost decompression architecture that combine the advantages of both symbol-based and linear-based techniques and offer a very attractive unified solution that removes the barriers of existing test data compression techniques. Besides the traditional goals of high compression and short test application time, the proposed method also offers low shift switching activity and high unmodeled defect coverage at the same time. In addition, it favors multi-site testing as requires a very low pin-count interface to the automatic test equipment. Finally, contrary to existing techniques, it provides an integrated solution for testing multi-core system on chips (SoCs) as it is suitable for cores of both known and unknown structures that usually coexist in SoCs. Liaperdos, J. ; Arapoyanni, A. ; Tsiatouhas, Y. Adjustable RF Mixers' Alternate Test Efficiency Optimization by the Reduction of Test Observables http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6582596 A method for the optimization of the efficiency of alternate tests for adjustable RF mixers is presented in this paper. Alternate tests provide a cost- and time-effective substitute for their conventional specification-based counterparts by attempting to predict rather than directly measuring a circuit's performance from its response to suitable test stimuli. In order to provide post-manufacture yield recovery through calibration, integrated RF circuitsÑespecially nanometric circuitsÑare often designed to present some form of adjustability. Such a property offers a set of discrete states of operation, from which a performance-compliant state is selected by calibration. In general, an alternate test can be conducted for each discrete state of operation, thus providing a large set of test observables from which regression models can be constructed to predict performance in all available states. However, test time and cost concerns impose that the derivation of the predictive models should be performed through an optimization procedure that aims to select a subset of the test observables that minimizes a certain cost criterion. In this paper, alternate tests for adjustable RF mixers are considered where the test response consists of dc voltage levels that appear at certain circuit nodes while the mixer operates in homodyne mode. Selection algorithms are applied to determine the optimum observables from the test response. Simulations on a typical RF mixer, designed in an 0.18um CMOS technology, have shown significant improvement in the corresponding alternate test efficiency. Karimi, N. ; Chakrabarty, K. Detection, Diagnosis, and Recovery From Clock-Domain Crossing Failures in Multiclock SoCs http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6582582 Clock-domain crossing (CDC) faults require careful post-silicon testing for multiclock circuits. Even when robust design methods based on synchronizers and design verification techniques are used, process variations can introduce subtle timing problems that affect data transfer across clock-domain boundaries for fabricated chips. We integrate solutions for detecting and locating CDC faults, and ensuring post-silicon recovery from CDC failures. In the proposed method, CDC faults are located using a CDC-fault dictionary, and their impact is masked using post- silicon clock-path tuning. To quantify the impact of process variations in the transfer of data at clock domain boundaries of multiclock circuits and to validate the proposed error-recovery method, we conducted a series of HSpice simulations using a 45-nm technology. The results demonstrate high incidence of process variation-induced violation of setup and hold time at the boundary flip-flops, even when synchronizer flip-flops are employed. The results also confirm the effectiveness of the proposed error-recovery scheme in recovering from CDC failures. VERIFICATION Lv, J. ; Kalla, P. ; Enescu, F. Efficient Gröbner Basis Reductions for Formal Verification of Galois Field Arithmetic Circuits http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6582606 Galois field arithmetic is a critical component in communication and security-related hardware, requiring dedicated arithmetic architectures for better performance. In many Galois field applications, such as cryptography, the data- path size in the circuits can be very large. Formal verification of such circuits is beyond the capabilities of contemporary verification techniques. This paper addresses formal verification of combinational arithmetic circuits over Galois fields of the type BBF_2^k using a computer-algebra/algebraic-geometry-based approach. The verification problem is formulated as membership testing of a given specification polynomial in a corresponding ideal generated by the circuit constraints. Ideal membership testing requires the computation of a Gröbner basis, which is computationally very expensive. To overcome this limitation, we analyze the circuit topology and derive a term order to represent the polynomials. Subsequently, using the theory of Gröbner bases over BBF_2^k, we show that this term order renders the set of polynomials itself a minimal Gröbner basis of this ideal. Consequently, the verification test reduces to a much simpler case of Gröbner basis reduction via polynomial division, significantly enhancing verification efficiency. To further improve our approach, we exploit the concepts presented in the F4 algorithm for Gröbner basis, and show that the verification test can be formulated as Gaussian elimination on a matrix representation of the problem. Finally, we demonstrate the ability of our approach to verify the correctness of, and detect bugs in, up to 163-bit circuits in BBF_2^163Ñwhereas verif- cation utilizing contemporary techniques proves infeasible. Chung, Y.-T. ; Jiang, J.-H.R. Functional Timing Analysis Made Fast and General http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6582561 In contrast to structural timing analysis, functional timing analysis for circuit delay computation is accurate, but computationally expensive in refuting false critical paths. Despite recent progress on satisfiability-based functional timing analysis, the formulation generality and computation efficiency remain room for further improvement. This paper provides a unified view on different notions of timed characteristic functions and efficient transformation for satisfiability solving. Experimental results show that functional timing analysis on industrial designs can be made up to several orders of magnitude faster and more generally applicable than prior methods. SHORT PAPERS Ye, Z. Noise Companion State-Space Passive Macromodeling for RF/mm-Wave Circuit Design http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6582573 Automatic macromodeling for passive linear systems is useful in RF/mm-wave circuit designs. Traditional macromodeling approaches only capture the port parameters of the systems, enabling small-signal (AC) and large- signal (transient, PSS, etc) analyses, but lack the capability of noise modeling which is very important in RF/mm- wave circuit designs. In this letter, we propose to account for noise in a traditional state-space-based passive macromodeling method. The proposed approach is to generate a noise companion model that describes the noise behavior in addition to a traditional state-space model that describes the port parameters. The proposed model supports small-signal noise analysis, periodic noise analysis, and large-signal transient noise analysis. In addition, the proposed model can work with commercial simulators seamlessly without modification to the simulator. Examples validate the proposed modeling method. Huang, L.-R. ; Huang, S.-Y. ; Sunter, S. ; Tsai, K.-H. ; Cheng, W.-T. Oscillation-Based Prebond TSV Test http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6582613 Testing the quality of prebond through-silicon vias (TSV) is a vital part of the Known-Good-Die test that is often necessary to retain a high compound yield for 3-D stacked integrated circuits. In this paper, we present a versatile prebond TSV test method applicable before wafer thinning when the deep end of the TSV is inaccessible as buried in the still-thick wafer. Technical merits include: 1) the ability to handle both the resistive open fault and the leakage fault in the same test structure; 2) a capability that allows an user to have a better measure of the severity of the fault; and 3) an all-digital and easy to implement design-for-testability circuit. Pomeranz, I. Functional Broadside Tests With Incompletely Specified Scan-In States http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6582599 Functional broadside tests address overtesting of delay faults by using reachable states as scan-in states. Since reachable states are, in general, fully specified, functional broadside tests are not amenable to the commonly used test data compression methods. This paper defines multicycle functional broadside tests whose scan-in states are incompletely specified. The first clock cycles of a test bring the circuit from the scan-in state into a reachable state without activating delay faults. The last two clock cycles detect delay faults by applying a two-cycle functional broadside test. This paper also describes a test generation procedure for tests of this type. The procedure uses a condition, which is based on the initial state of the circuit for functional operation, to simplify the generation of the tests.