Dong Jiao

I am a Ph.D. student in Department of Electrical and Computer Engineering at the University of Minnesota, Twin Cities. My research interests include power integrity for mixed-signal ICs and low-power designs. I am a member of Minnesota VLSI Research Group and affiliated with Department of Electrical and Computer Engineering (ECE). My advisor is Prof. Chris Kim.

Education

• 02/2009-present               University of Minnesota, Twin Cities, USA
• Ph.D.      Electrical & Computer Engineering    (GPA: 3.92)

• 09/2006-02/2009              University of Minnesota, Twin Cities, USA
• M.S.        Electrical & Computer Engineering    (GPA: 4.0)

• 09/2002-07/2006             Tsinghua University, Beijing, China
• B.E.         Electronic Engineering    (GPA: 93/100)

Research & Chip Designs Involved In

• Power delivery and supply noise regulation
• Adaptive clocking and PLL
• Switched capacitor DC/DC converter
• Low power on-chip process, voltage, temperature and reliability monitors
• 3D IC and SRAM design

Intern Experience

• 10/2010-06/2011          Samsung Semiconductor Inc., San Jose, CA, USA
  
• 05/2008-08/2008        Seagate LLC., Bloomington, MN, USA
  

Selected Awards and Honors

• Research Fellowship from the University of Minnesota, Twin Cities, 2006
• Honor Graduates of Tsinghua University, 2006
• Consecutive Scholarships from Tsinghua University, in 2003, 2004 and 2005

Publications

1. Dong Jiao, Bongjin Kim and Chris H. Kim, "A Programmable Adaptive Phase-Shifting PLL for Enhancing Clock Data Compensation under Resonant Supply Noise," In SRC Techcon 2011 (Techcon'11) (to appear)


2. Pingqiang Zhou, Dong Jiao, Chris H. Kim and Sachin Sapatnekar, "Exploration Of On-Chip Switched-Capacitor DC-DC Converter For Multicore Processors Using A Distributed Power Delivery Network," In Custom Integrated Circuits Conference 2011 (CICC'11) (accepted)


3. Pulkit Jain, Dong Jiao, Xiaofei Wang and Chris Kim, "Measurement, Analysis and Improvement of Supply Noise in 3D ICs," VLSI Circuits Symposium, Jun. 2011 [Paper][Slides]


4. Dong Jiao, and Chris Kim, "A Programmable Adaptive Phase-Shifting PLL for Enhancing Clock Data Compensation under Resonant Supply Noise," International Solid-State Circuits Conference (ISSCC), Feb. 2011 [Paper][Slides]


5. Dong Jiao, Jie Gu, and Chris Kim, "Circuit Design and Modeling for Enhancing the Clock Data Compensation Effect under Resonant Supply Noise," IEEE Journal of Solid-State Circuits (JSSC), Oct. 2010 [Paper]


6. Dong Jiao, Jie Gu, and Chris Kim, "Circuit Techniques for Enhancing the Clock Data Compensation Effect under Resonant Supply Noise," In Custom Integrated Circuits Conference 2009 (CICC'09), San Jose, California, 2009 [Paper][Slides]


7. Dong Jiao, Jie Gu, Pulkit Jain, and Chris Kim, "Enhancing Beneficial Jitter Using Phase-Shifted Clock Distribution," In International Symposium on Low Power Electronics and Design 2008 (ISLPED'08), Bangalore, India, 2008 [Paper][Slides]


8. Dong Jiao, Helen Li, Ran Wang, Henry Huang, and Yiran Chen, "Integrated Circuit Active Power Supply Regulation," U.S. Patent, 12/501,375

Course Work

• EE 8337, Analog Circuits for Wired/Wireless Communications, Spring 2010
• Project: Differential LNA and I/Q mixer designs for IEEE 802.11g
• EE 5327, VLSI Design Laboratory, Spring 2009
• Project: Parallel LCPC encoder and decoder designs using Verilog
• CSCI 5421, Advanced Algorithms and Data Structure, Fall 2008
• EE 5324, VLSI Design II, Spring 2008
• Project: Schematic and layout design of a 16k SRAM using 3DIC process
• EE 5164, Semiconductor Properties and Devices II, Spring 2008
• EE 5323, VLSI Design I, Fall 2007
• Project: Schematic and layout design of a 16-bit carry look-ahead adder
• EE 5163, Semiconductor Properties and Devices I, Fall 2007
• EE 5364, Advanced Computer Architecture, Fall 2007
• EE 5302, VLSI CAD II, Spring 2007
• CSCI 5302, Numerical Analysis, Spring 2007
• EE 5333, Analog Integrated Circuits Design, Fall 2006
• Project: Schematic and layout design of a second order Sigma-Delta AD converter including an ultra low power OTA
• EE 5301, VLSI CAD I, Fall 2006

Links

• Shuo Guo