Plan B Project Ideas

The following is a brief description of plan B projects that I am willing to advise. For related research topics, you can refer to my research page.

  1. Adding memory access characterization to the Machine SUIF compiler.
    The goal of this project is to add memory access analysis / optimization to the Machine SUIF C compiler targeting small on-chip memory blocks. It is crucial for reconfigurable computing system design (and hardware/software codesign in general) to carefully partition the array variables in a program to different memory blocks (on-chip and off-chip) in the system. The first step to facilitate the memory partitioning process is to analyze the access patterns of each of the variables.
    Required skills: C programming (esp large code sizes), knowledge of computer architecture, understanding of cache structures.
    Related paper(s):
  2. Optimizing memory usage and developing VHDL modules for memory instantiation on the Xilinx Virtex XCV1000E Chip.
    An important step in implementing applications on the Xilinx Virtex chip is to setup on-chip memory blocks and to provide communication standards for data-transfer between the host processor and the FPGA chip. We have a top-of-the-line FPGA board from Annapolis Micro Systems that features one Virtex FPGA chip, in addition to plenty of on-board RAM, etc. We will use this board as the target platform for implementing the VHDL modules that we write for this project.
    In this project we will study the Virtex RAM blocks, and will research different methods of communicating with them. We will research the area / speed trade-off of different memory configuration options.
    Required skills: VHDL programming
    Related papers and links:
  3. Implementing an image processing algorithm on the Annapolis FireBird FPGA board.
    The goal of this project is to implement an image filtering algorithm on the Annapolis FireBird FPGA board that we have. A significant part of the project will be understanding how the board works and how to implement designs using its template VHDL models.
    Required skills: VHDL programming

  4. Developing runtime support systems for dynamically reconfigurable systems
    Reconfigurable systems exploit FPGA chips to adapt the hardware to the running application by configuring the FPGA with a suitable mix of functional units (adders, multipliers, etc.) to minimize rutnime of the program. Runtime reconfigurable systems do so in the middle of application execution. JBits is a tool that allows runtime reconfiguration of the Xilinx Virtex chip. We will write some API on top of JBits to provide on-the-fly placement of new functional units, caching of hardware resources and so on.
    Required skills: Java programming, knowledge of Operating Systems
    Related papers and links: