| Fabricaion for 3D chips is now a reality and will soon be a
common practice.
- Cristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal,
Tianpei
Zhang, Kia Bazargan, and Sachin S. Sapatnekar, "Placement
and Routing in 3D Integrated Circuits", IEEE Design and Test, to
appear.
- Cristinel Ababei, Hushrav Mogal, and Kia Bazargan,
"Three-dimensional
Place and Route
for FPGAs", IEEE
Transactions on Computer-Aided Design of Integrated Circuits and
Systems (TCAD), to appear.
- C. Ababei, H. Mogal, and K. Bazargan, "Three-dimensional
Place
and Route for FPGAs", Asia
South-Pacific Design Automation Conference (ASPDAC), 2005.
To download TPR, go to the Downloads page
and search TPR.
The Java visualization tool is called ParGUI.
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Last updated Aug 31, 2004
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