3D Chip: Mixed-Signal Design Based on MIT-LL 3D Technology

 In collaboration with Prof. Harjani's group, we designed a mixed-signal chip based on MIT Lincoln Lab's 3D IC technology. Our chip has three active device layers as shown in the figure (click on the image for a more detailed view). Tiers A and B contain digital logic, and Tier C has a mixture of digital and analog blocks. (Tier refers to one active device layer and three metal layers).

Since we had very short design time, we opted for a regular fabric (array of tiles), and made the tiles reconfigurable to maximize design flexibility and robustness. Tier A consists of a 6x6 array of tiles, and tiers B and C each contain an array of 3x6 tiles. Half of Tier B forms part of the Faraday cage that encloses the analog circuits, which in are placed on half of Tier C.

The figure on the left shows the schematic of Tier A. The global connections are shown in green, red  and black:

• Global control signals form a configuration chain that visits every tile. The chain contains global signals like such as clock divider signal, reset, and mode of operation, as well as a long serial SRAM chain that configures individual tiles.
  
• The Thermal sensor tree connects to the diodes at the center of every tile. The diode is connected to the tree through an SRAM-programmable switch. The root of the tree is connected to an I/O pad. By connecting only one tile's PN-junction to the tree, we can use an off-chip current source and monitor the voltage at the root of the tree. The voltage correlates with the temperature at the tile that is connected to the tree.
  
• Busses: Each tile connects to three busses on each side: left, right, top and bottom. The switchbox inside each tile makes nearest-neighbor connections between these busses. The switchbox is SRAM programmable and similar to the switchbox used in the Xilinx 4000 series.. Of the three busses on each side, one is 3D, i.e., has connections to the switchbox exactly above it on Tier B. Similarly, 3D switches in Tier B connect to their counterparts in tiers A and C.

The architecture of the tile is shown in this figure. Each tile has a logic and a switchbox component. The logic part has a 16-bit multiplier, a 16-bit adder and hardwired constant inputs. The unit can perform addition, multiplication and multiply-add operations. The input could be routed either from a programmable register, the busses, or hardwired constants. A clock divider can change the frequency of the main clock. A failsafe second clock is also provided that controls the frequency of toggling hardwired inputs.

The Switchbox is similar to the Xilinx 4000 series FPGA switchbox and makes nearest-neighbor connections. The ring oscillator can be turned on or off using an SRAM-programmable switch. The purpose of the oscillator is to generate noise for the analog circuit and study the shielding techniques that we have used. Each bus can connect to any logic block input or output. A bus can also pass through a tile without connecting to the input or output of the tile.