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Last updated: Oct 24, 2006

KIA BAZARGAN

Department of Electrical and Computer Engineering	Phone: (612) 625-4588
University of Minnesota	Fax: (612) 625-4583
200 Union Street SE	Email: kia@umn.edu
Minneapolis, MN 55455	http://www.ece.umn.edu/users/kia

Education

2000	Ph.D., Electrical and Computer Engineering, Northwestern University, August 2000, Thesis title: "Designing CAD Tools for Reconfigurable Computing Systems" Advisor: Prof. Majid Sarrafzadeh.
1998	M.S., Electrical and Computer Engineering, Northwestern University, June 1998. Thesis title: "Floorplanning for Uncertain Designs". Advisor: Prof. Majid Sarrafzadeh.
1996	B.S., Computer Science, Sharif University of Technology, June 1996, Tehran, Iran.

Appointments

Fall 2006 - present Associate Professor, Dept. of Electrical and Computer Engineering, Univ. of Minnesota.

Fall 2000 - 2006 Assistant Professor, Dept. of Electrical and Computer Engineering, Univ. of Minnesota.

Jan. 1997 - July 2000 Research Assistant, Northwestern University

Research activities: Developed a new floorplanning paradigm to handle design uncertainty by minimizing the variance of the final floorplan area; developed algorithms for on-the-fly and offline floorplanning of reconfigurable computing systems; developed very fast floorplanning algorithms; implemented a high-level synthesis tool to convert C programs to HDL and floorplan the design for reconfigurable computing.

Teaching activities: taught undergraduate students EE-B01 “Introduction to Logic Design” in the summer of 1997. Was a TA for the course EE-C57 “VLSI Physical Design”.

Summer 98 Summer internship, Monterey Design Systems, Sunnyvale, California.
I worked on interaction of synthesis and physical design, and some of their physical design algorithms.

Awards

Recipient of the NSF CAREER award, 2003 .
Best paper award nominee, Design Automation Conference, 2000, 2002, 2003.

Publications

Please refer to publications page for the most up to date list.

Journal Publications

(Kia’s students are marked with an asterisk*)
J1.   Gang Wang, Satish Sivaswamy*, Cristinel Ababei*, Kia Bazargan, Ryan Kastner and Eli Bozorgzadeh, " Statistical Analysis and Design of HARP Routing Pattern FPGAs ", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 2088-2102, Vol. 25, No. 10, October 2006. .

J2.   Cristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, and Sachin S. Sapatnekar, " Placement and Routing in 3D Integrated Circuits ", IEEE Design and Test , Vol. 22, No. 6, pp. 520-531, Nov-Dec 2005.

J3.    Jinghuan Chen, Kia Bazargan, and Jaekyun Moon, “A Reconfigurable FPGA-Based Readback Signal Generator for Hard-Disk Read Channel Simulator”, IEEE Transactions on Very Large Scale Integration Systems, under review.

J4.    Ying Chen, Karthik Ranganathan*, Vasudev V Pai*, David J. Lilja, and Kia Bazargan, "A Novel Memory Structure for Embedded Systems: Flexible Sequential and Random Access Memory", Journal of Computer Science and Technology (JCST), 2005.

J5.    Cristinel Ababei*, Hushrav Mogal*, and Kia Bazargan, "Three-dimensional Place and Route for FPGAs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, to appear.

J6.    P. Maidee*, C. Ababei* and K. Bazargan, “Timing-driven Partitioning-based Placement for Island Style FPGAs”, IEEE Transactions on Computer Aided Design, Vol. 4, No. 3, pp. 1744 - 1750, Mar 2005.

J7.    C. Ababei* and K. Bazargan, "Non-Contiguous Linear Placement for Reconfigurable Fabrics", International Journal of Embedded Systems, esp. issue on Reconfigurable Architectures Workshop (RAW), Inderscience Publishers, 2004.

J8.    J. Chen, J. Moon and K. Bazargan, “FPGA-based Reconfigurable Generation of Readback Signals”, IEEE Transactions on Magnetics, Vol. 4, No. 3, pp. 1744 - 1750, May 2004.

J9.    A. Ranjan, K. Bazargan, S. Ogrenci and M. Sarrafzadeh, "Fast Floorplanning for Effective Prediction and Construction ", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 9, Issue 2, pp. 341-351, April 2001.

J10.    K. Bazargan, R. Kastner and M. Sarrafzadeh, "3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems", Design Automation for Embedded Systems (DAfES) - RSP'99 Special Issue, April 2000.

J11.    K. Bazargan, R. Kastner and M. Sarrafzadeh, "Fast Template Placement for Reconfigurable Computing Systems", IEEE Design and Test - Special Issue on Reconfigurable Computing, pp. 68-83, January-March 2000.

J12.    K. Bazargan, S. Kim and M. Sarrafzadeh, "Nostradamus: A Floorplanner of Uncertain Designs", IEEE Transactions on Computer-Aided Design (TCAD), pp. 389-397, April 1999.

Book Chapters

B1. Kia Bazargan, "Chapter 10.2: FPGA Technology Mapping, Placement, and Routing", in The Handbook of Algorithms for VLSI Physical Design Automation, Charles J. Alpert, Dinesh P. Mehta, and Sachin S. Sapatnekar, CRC Press.

B2. Sachin Sapatnekar, Kia Bazargan, "Chapter 10.4: 3D Design", in The Handbook of Algorithms for VLSI Physical Design Automation, Charles J. Alpert, Dinesh P. Mehta, and Sachin S. Sapatnekar, CRC Press.

Refereed Conference Publications

(Presenter’s name is underlined, Kia’s students are marked with an asterisk*)

C1.    Satish Sivaswamy*, Gang Wang, Cristinel Ababei*, Kia Bazargan, Ryan Kastner, Eli Bozorgzadeh, "HARP: Hardwired Routing Pattern FPGAs", International Symposium on Field Programmable Gate Arrays (FPGA), 2005.
[full paper acceptance rate: 24 out of 97]

C2.    C. Ababei*, H. Mogal*, and K. Bazargan, "3D FPGAs: Placement, Routing and Architecture Evaluation", International Symposium on Field Programmable Gate Arrays (FPGA), (poster), 2005.

C3.    C. Ababei*, H. Mogal*, and K. Bazargan, "Three-dimensional Place and Route for FPGAs", Asia South-Pacific Design Automation Conference (ASPDAC), 2005. [full paper acceptance rate: 14%]

C4.    C. Ababei*, and K. Bazargan, "Exploring Potential Benefits of 3D FPGA Integration", Field-Programmable Logic and its Applications (FPL), 2004.

C5.    Y. Chen, K. Ranganathan*, V. V. Pai*, D. Lilja and K. Bazargan, "Enhancing the Memory Performance of Embedded Systems with the Flexible Sequential and Random Access Memory", Asia-Pacific Computer Systems Architecture Conference (ACSAC), 2004.

C6.    W. Choi* and K. Bazargan, “Incremental Placement for Timing Optimization”, International Conference on Computer-Aided Design (ICCAD), 2003. [acceptance rate: 26.32% (according to this)]

C7.    C. Ababei* and K. Bazargan, “Placement Method Targeting Predictability, Robustness and Performance”, International Conference on Computer-Aided Design (ICCAD), p., 2003. [acceptance rate: 26.32% (according to this)]

C8.    P. Maidee*, C. Ababei* and K. Bazargan,        (nominated for the best paper award)
”Fast Timing-driven Partitioning-based Placement for Island Style FPGAs”, Design Automation Conference (DAC), pp. 598-603, 2003. [acceptance rate: 24% (according to this)]

C9.    K. Bhasyam* and K. Bazargan, "HW/SW Codesign Incorporating Edge Delays Using Dynamic Programming", Euromirco Symposium on Digital Systems Design, p., 2003.

C10.    V. K. Marreddy*, S. Noorbaloochi* and and K. Bazargan, "Linear Placement for Static / Dynamic Reconfiguration in JBits", IEEE Symposium on FPGAs for Custom Computing Machines (FCCM), p., 2003. (poster)

C11.    W. Choi* and K. Bazargan, "Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration", Design Automation and Test in Europe (DATE), p., 2003. (short paper) [acceptance rate: 25.76% (according to this)]

C12.    C. Ababei* and K. Bazargan, "Timing Minimization by Statistical Timing hMetis-based Partitioning", VLSI Design, pp. 58-63, 2003.

C13.    C. Ababei*, N. Selva, K. Bazargan and G. Karypis, ”Multi-objective Circuit Partitioning for Cutsize and Path-Based Delay Minimization”, International Conference on Computer-Aided Design (ICCAD), 2002. [acceptance rate: 27.55% (according to this)]

C14.    J. Chen, J. Moon and K. Bazargan,            (nominated for the best paper award)
“A Reconfigurable FPGA-Based Readback Signal Generator For Hard-Drive Read Channel Simulator”, Design Automation Conference (DAC), pp. 349-354, 2002. [acceptance rate: 30% (according to this)]

C15.    C. Ababei* and K. Bazargan, "Statistical Timing Driven Partitioning for VLSI Circuits", Design Automation and Test in Europe (DATE), p. 1109, 2002. (poster)

C16.    K. Bazargan, S. Ogrenci and M. Sarrafzadeh,        (nominated for the best paper award)
"Integrating Scheduling and Physical Design into a Coherent Compilation Cycle for Reconfigurable Computing Architectures", Design Automation Conference (DAC), pp. 635-640, 2000.

C17.    A. Ranjan, K. Bazargan and M. Sarrafzadeh, "Fast Hierarchical Floorplanning with Congestion and Timing Control", IEEE International Conference on Computer Design (ICCD), pp. 357-362, September 2000.

C18.    K. Bazargan, R. Kastner, S. Ogrenci and M. Sarrafzadeh, "A C to Hardware/Software Compiler", IEEE Symposium on FPGAs for Custom Computing Machines (FCCM), pp. 331-332, 2000. (poster)

C19.    K. Bazargan, A. Ranjan and M. Sarrafzadeh, "Fast and Accurate Estimation of Floorplans in Logic/High-level Synthesis", Great Lakes Symposium on VLSI (GLSVLSI), pp. 95-100, March 2000.

C20.    A. Ranjan, K. Bazargan and M. Sarrafzadeh, "Floorplanner 1000 Times Faster: A Good Predictor and Constructor", in System-Level Interconnection Prediction (SLIP), pp. 115-120, 1999.

C21.    K. Bazargan and M. Sarrafzadeh, "Fast Online Placement for Reconfigurable Computing Systems", IEEE Symposium on FPGAs for Custom Computing Machines (FCCM), pp. 300-302, 1999. (poster)

C22.    K. Bazargan, S. Kim and M. Sarrafzadeh, "Nostradamus: A Floorplanner of Uncertain Designs", International Symposium on Physical Design (ISPD), pp. 18-23, 1998.

Workshops

(All except W3 are peer reviewed. Presenter’s name is underlined, Kia’s students are marked with an asterisk*)
W1.    C. Ababei* and K. Bazargan, "Non-Contiguous Linear Placement for Reconfigurable Fabrics", Reconfigurable Architectures Workshop (RAW), p., 2004.

W2.    S. Ogrenci, K. Bazargan and M. Sarrafzadeh, "Image analysis and partitioning for FPGA implementation of image restoration", in Proceedings of the IEEE Workshop on Signal Processing Systems, pp. 346-355, 2000.

W3.    K. Bazargan and M. Sarrafzadeh, "Fast Scheduling and Placement Methods for C to Hardware/Software Compilation", SPIE International Symposium on Information Technologies, Vol. 4212, November 2000.

W4.    R. Kastner, K. Bazargan and M. Sarrafzadeh, "Physical Design for Reconfigurable Computing Systems using Firm Templates", Workshop on Reconfigurable Computing (WoRC), pp. 19-26, 1999.

W5.    K. Bazargan, R. Kastner and M. Sarrafzadeh, "3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems", 10th IEEE International Workshop on Rapid System Prototyping (RSP' 99), pp. 38-43, 1999.

Invited Talks

I1.    Satish Sivaswamy, Kia Bazargan, “Pre-routed Patterns for Structured ASIC Designs”, LSI Logic, Bloomington, MN, June 2005.

I2.    Kia Bazargan, “3D CAD for FPGAs”, IBM T.J. Watson, NY, Apr 2005.

I3.    Kia Bazargan, “Better Field Programmable Gate Arrays (FPGAs)? CAD and Architectural Innovations Will Do the Trick!”, ECE Dept., University of Minnesota, Apr 2005.

I4.    Kia Bazargan, "HARP: Hardwired Routing Pattern FPGAs", Xilinx Corporation, San Jose, CA, Feb 2005.

I5.    Kia Bazargan, “Partitioning-Based Timing-Driven Placement for 2D and 3D FPGAs”, ECE Dept., Northwestern University, Dec 2003.

Synergic Activities

Associate Editor, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Dec 2004-present
Guest Editor (with Andre' DeHon of Caltech), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) special issue on FPGA conference 2006
Guest Editor (with John Lach of U of Virginia), ACM Transactions on Embedded Computing Systems (ACM TECS), Vol. 3, No. 2, May 2004.
Member of the Technical Program Committee:
- Design Automation Conference, 2007.
- ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2006. (and session chair), 2007
- International Conference on Computer Aided Design (ICCAD), 2004, 2003 (and session chair), 2002 (and session chair).
- Asia South Pacific Design Automation Conference (ASP-DAC), 2004.
- Great Lakes Symposium, 2003, 2002.
- Engineering of Reconfigurable Systems and Algorithms, 2003.
- International Symposium on Physical Design (ISPD), 2002 (and session chair).
Organizer and presenter of a tutorial in ICCAD’02 titled “FPGAs: Computer-Aided Design, Applications and Future Architectures”
Participant in “NSF Workshop on Nanocomputing”, Carnegie Mellon University. (http://www-2.cs.cmu.edu/~phoenix/nanocomputing/), 2002. The purpose of the workshop was to come up with recommendations for NSF on the best directions the nano technology research should take to get Computer Scientists more involved in research related to nano-technology.
Participant in three NSF review panels. (CAREER, Physical Design) 2004-2005
Reviewer of UC Micro proposals 2003, 2005
Journal Referee: Reviewer for:
- IEEE Transactions on Computer Aided Design (TCAD) 1999-2005.
- IEEE Transactions on VLSI Systems (TVLSI) 2003-2005.
- IEEE Transactions on Parallel and Distributed Systems (TPDS) 2000.
- IEEE Transactions on Design Automation of Electronic Systems (TODAES).2001, 2003-2005.
Conference Referee: DAC, ISPD, ICCAD, ERSA, GLSVLSI, ISCAS

Education Activities and Accomplishments

Course Development / Teaching

Course development and teaching of EE8950: Advanced Topics in ECE: Reconfigurable Computing, ECE Dept., U. of Minnesota, Spring 2003, 2006, (http://www.ece.umn.edu/users/kia/Courses/EE8310/index.html).
Course development and teaching of EE5324: VLSI Design II, ECE Dept., U. of Minnesota, Spring 2001-2006, (http://www.ece.umn.edu/users/kia/Courses/EE5324/index.html).
Course development and teaching of EE5301: VLSI Design Automation I, ECE Dept., U. of Minnesota, Fall 2001-2005, (http://www.ece.umn.edu/users/kia/Courses/EE5301/index.html).

Past Students

Cristinel Ababei, thesis title: “Design Automation for Physical Synthesis of VLSI Circuits and FPGAs”, Dec 2004, now with Magma Design Automation
Wonjoon Choi, thesis title: “Performance Driven Optimization of VLSI Layout”, Sep 2005, will join Sun Microsystems.

M.S.

Zhen Chen, Thesis Topic: Parallel implementation of a second-order implementation of the Volterra filter. 2006.
Yi Ding. Thesis Topic: Implementing a third-order Volterra filter for Ultrasound imaging. 2006.
Dereje Yilma, MS Plan B, “Implementing the ‘Separable’ Second Order Volterra Filter In Xilinx Virtex-E FPGA”, June 2005, now with IBM Rochester.
Vinil Sharma, MS Plan B, “Flexible Sequential Random Access Memory”, Dec 2004.
Anatoli Glagolev, MS Plan B, “Floating-Point Division and Square Root on Xilinx Virtex-E FPGA”, Dec 2004, now with Microsoft.
Girish Venkatraman, MS Plan B, “ FPGA based Implementation and Analysis of Flexible Sequential Access Memory”, May 2004.
Karthikeyan Bhasyam, MS Plan B, “Algorithms for Resource Assignment and Scheduling in High-Level Synthesis”, May 2003, now with Qualcom.
Karthik Ranganathan, MSEE, “Flexible Sequential Access Memory”, May 2003, now with Cypress Semiconductor.
Paul Kern, MS Plan B, “A Microcontroller-Based Heating and Cooling Control System”, May 2003, now with Honeywell.
Ranjit Eswaran, MS Plan B, 2003, now with Intel.
Vamsi-Krishna Reddy Mareddy, MS Plan B, “A fast Run-Time Placement algorithm for Partial & Dynamically Reconfigurable FPGAs”, July 2003, now with Pfizer.
Pongstorn Maidee, “Timing-Driven Partitioning-Based Placement for Island Style FPGAs”, Oct 2003.
Michael A. Hinterberg, MS Plan B, “Reconfigurable Graphics Pipeline on Annapolis Firebird”, Summer 2002, now with HP.
Varun Kharbanda, MS Plan B, “Implementing a Signal Processing Algorithm on the Annapolis FireBird FPGA Board”, May 2002.
Cristinel Ababei, MS Plan A, “Statistical Timing Driven Partitioning”, May 2002.
SeongHo Song, MS Plan B, “GOST Algorithms implementation using VHDL”, Summer 2002.
Joseph S. Mollen, MS Plan B, “Hardware Independent Delay and Power Calculation Modules”, Dec 2001, now with IBM Rochester.
Saed Wadi, “High Speed Phase-Locked Loop Used in VCSEL Driver Chip”, May 2001, with Honeywell.

Undergraduate

(Senior Honors Program) John Engleman, “Hardware Operating System Support for Reconfigurable Computing”, Academic year 2005-2006.
(Senior Honors Program) Joe Strommen, “Steiner Routing for FPGA Circuits”, Academic year 2004-2005.
(NSF REU) James D. Foltz, “PRGUI: A Visual Tool For Displaying Placement and Routing”, Summer 2004.
(UMN UROP) Sharareh Noorbaloochi, “Compiling Datapath Expressions to JBits Compatible Hardware Implementation”, 2002.
(Summer REU) Seth Sweep, “Using JBits as an Interface for Field Programmable Gate Arrays (FPGAs)”, 2002.
(Senior Honors Program) Matthew Tilstra, “Developing a Hardware Cache Manager for Reconfigurable Computing Platforms”, 2001

Current Students

Pongstorn Maidee. Thesis Topic: Next generation FPGA placement and routing algorithms. Expected Graduation: June 2006.
Hushrav Mogal. Thesis Topic: Placement and reconfiguration methods to mitigate thermal issues in 2D and 3D FPGAs. Expected Graduation: June 2008.
Satish Sivaswamy. Thesis Topic: Advanced FPGA and structured-ASIC architectures. Expected Graduation: June 2008.

M.S.

Krishnacumar Vasudevan, “Adaptive Cubic Voltera Implementation”, 2006.

Fall 2006 - present	Associate Professor, Dept. of Electrical and Computer Engineering, Univ. of Minnesota.
Fall 2000 - 2006	Assistant Professor, Dept. of Electrical and Computer Engineering, Univ. of Minnesota.
Jan. 1997 - July 2000	Research Assistant, Northwestern University Research activities: Developed a new floorplanning paradigm to handle design uncertainty by minimizing the variance of the final floorplan area; developed algorithms for on-the-fly and offline floorplanning of reconfigurable computing systems; developed very fast floorplanning algorithms; implemented a high-level synthesis tool to convert C programs to HDL and floorplan the design for reconfigurable computing. Teaching activities: taught undergraduate students EE-B01 “Introduction to Logic Design” in the summer of 1997. Was a TA for the course EE-C57 “VLSI Physical Design”.
Summer 98	Summer internship, Monterey Design Systems, Sunnyvale, California. I worked on interaction of synthesis and physical design, and some of their physical design algorithms.