Book Chapters:

  1. K.K. Parhi, and M. Hatamian, "A High Sample Rate Recursive Filter Chip", in VLSI Signal Processing III, Chapter 1, IEEE Press, (Proc. of the Third IEEE VLSI Signal Processing Workshop), Monterey, CA, Nov. 1988, pp. 3-14
  2. K.K. Parhi, and G. Shrimali, "A Concurrent Loss-Less Coder for Video Compression", in VLSI Signal Processing V, IEEE Press, Oct. 1992 (Proc. of the Fifth IEEE VLSI Signal Processing Workshop, Napa Valley, CA), pp. 257-266
  3. K.K. Parhi, "Parallel Processing and Pipelining in Huffman Decoder", (Chapter 12) in VLSI Implementations for Image Communications , Series Advances in Image Communications (Edited by Peter Pirsch), Vol. 2 , Elsevier Science Publisher, Amsterdam, 1993, pp. 365-395
  4. K.K. Parhi, "VLSI For Signal Processing: Special Architectures", in The Electrical Engineering Handbook , edited by Richard C. Dorf, CRC Press, 1993, pp. 370-384 (Chapter 17, Section 17.1)
  5. N.R. Shanbhag, and K.K. Parhi, "VLSI Implementation of a 100 MHz Pipelined ADPCM Codec Chip", in VLSI Signal Processing VI , IEEE Press, Oct. 1993 (Proc. of the sixth IEEE VLSI Signal Processing Workshop, Veldhoven, Netherlands), pp. 114-122
  6. C.Y. Wang, and K.K. Parhi, "The MARS High-Level DSP Synthesis System", in VLSI Design Methodologies for Digital Signal Processing Architectures , edited by M. Bayoumi, pp. 169-205, Kluwer Academic Press, 1994
  7. J.-G. Chung and K.K. Parhi, "Pipelined Wave Digital Filter Design for Narrow-Band Sharp-Transition Digital Filters", in VLSI Signal Processing VII , pp. 501-510, IEEE Press, Oct. 1994 (Proc. of the Seventh IEEE VLSI Signal Processing Workshop, La Jolla, CA)
  8. S. Jain and K.K. Parhi, "Efficient Power Based Galois Field Arithmetic Architectures", in VLSI Signal Processing VII , pp. 306-315, IEEE Press, Oct. 1994 (Proc. of the Seventh IEEE VLSI Signal Processing Workshop, La Jolla, CA)
  9. K.K. Parhi, "High-Level Transformations for DSP Synthesis", Chapter 8.1 in Microsystems Technology for Multimedia Applications: An Introduction , edited by B. Sheu et al. , IEEE ISCAS-95 Tutorial Book, pp. 575-587, IEEE Press, 1995
  10. N.R. Shanbhag and K.K. Parhi, "Pipelined Adaptive Digital Filters", Chapter 8.2 in Microsystems Technology for Multimedia Applications: An Introduction , edited by B. Sheu et al. , IEEE ISCAS-95 Tutorial Book, pp. 589-601, IEEE Press, 1995
  11. C.-Y. Wang and K.K. Parhi, "High-Level DSP Synthesis", Chapter 8.4 in Microsystems Technology for Multimedia Applications: An Introduction , edited by B. Sheu et al. , IEEE ISCAS-95 Tutorial Book, pp. 615-627, IEEE Press, 1995
  12. T.C. Denk and K.K. Parhi,"Systematic Design of Architectures for M-ary Tree-Structured Filter Banks", pp. 157-166, in VLSI Signal Processing VIII , IEEE Press, October 1995 (Proc. of the 1995 IEEE Workshop on VLSI Signal Processing, Sakai, Japan)
  13. K. Ito and K.K. Parhi,"Register Minimization in Cost-Optimal Synthesis of DSP Architectures", pp. 207-216, in VLSI Signal Processing VIII , IEEE Press, October 1995 (Proc. of the 1995 IEEE Workshop on VLSI Signal Processing, Sakai, Japan)
  14. K.K. Parhi and F. Catthoor, "Design of High-Performance DSP Systems", Chapter in Emerging Technologies: Designing Low-Power Digital Systems , Edited by R. Cavin and W. Liu, pp. 447-507, IEEE Press (ISCAS-96 Tutorial Book)
  15. L. Montalvo, K.K. Parhi, and J.H. Satyanarayana, "Estimation of Average Energy Consumption of Ripple-Carry Adder Based on Maximum Average Carry Chains", in VLSI Signal Processing IX , pp. 189-198, IEEE Press, October 1996 (Proc. of the 1996 IEEE Workshop on VLSI Signal Processing, San Francisco)
  16. K.K. Parhi, "Low-Power Digital VLSI Approaches", Chapter in Circuits and Systems in the Information Age , Edited by Y. Huang and C. Wei, pp. 3-22, IEEE Press, June 1997 (ISCAS-97 Tutorial Book)
  17. K.K. Parhi, "Video Compression", Chapter in Digital Signal Processing for Multimedia Systems , Edited by K.K. Parhi and T. Nishitani, Marcel Dekker, New York, 1999
  18. T.C. Denk and K.K. Parhi, "Wavelet VLSI Architectures", Chapter in Digital Signal Processing for Multimedia Systems , Edited by K.K. Parhi and T. Nishitani, Marcel Dekker, New York, 1999
  19. K.J. Raghunath and K.K. Parhi, "STAR RLS Adaptive Filtering", Chapter in Digital Signal Processing for Multimedia Systems , Edited by K.K. Parhi and T. Nishitani, Marcel Dekker, New York, 1999
  20. H.R. Srinivas and K.K. Parhi, "Division and Square-Root Processors", Chapter in Digital Signal Processing for Multimedia Systems , Edited by K.K. Parhi and T. Nishitani, Marcel Dekker, New York, 1999
  21. L. Song and K.K. Parhi, "Finite Field Arithmetic Architectures", Chapter in Digital Signal Processing for Multimedia Systems , Edited by K.K. Parhi and T. Nishitani, Marcel Dekker, New York, 1999
  22. J.H. Satyanarayana and K.K. Parhi, "Power Estimation Approaches", Chapter in Digital Signal Processing for Multimedia Systems , Edited by K.K. Parhi and T. Nishitani, Marcel Dekker, New York, 1999
  23. J. Ma and K.K. Parhi, "On Pipelined Implementations of QRD-RLS Adaptive Filters", Chapter in QRD-RLS Adaptive Filters Systems , Edited by J.A. Apolinario, Jr., pp. 269-297, Springer-Verlag, 2009

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