Refereed Conference Publications

1986

1. K.K. Parhi and R.S. Berkowitz, "False Alarm Threshold Setting in Complex Multi-Variate Systems using Importance Sampling Technique", Proceedings of the 29th Midwest Symposium on Circuits and Systems, Lincoln, Nebraska, August 1986, pp. 227-230
2. K.K. Parhi and D.G. Messerschmitt, "A Bit Parallel Bit Level Recursive Filter Architecture", Proceedings of the IEEE International Conference on Computer Design, October 6-9, 1986, Rye Town, Rye, NY, pp. 284-289

1987

1. K.K. Parhi and D.G. Messerschmitt, "Look-Ahead Computation: Improving Iteration Bound in Linear Recursions", Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing, Dallas, April 1987, pp. 1855-1858
2. K.K. Parhi and D.G. Messerschmitt, "Block Digital Filtering via Incremental Block-State Structure", Proceedings of the IEEE International Symposium on Circuits and Systems, Philadelphia, May 1987, pp. 645-648
3. K.K. Parhi, W.L. Chen, and D.G. Messerschmitt, "Architecture Considerations for High Speed Recursive Filtering",  Proceedings of the 1987 IEEE International Symposium on Circuits and Systems, Philadelphia, May 1987, pp. 374-377
4. K.K. Parhi and D.G. Messerschmitt, "Area-Efficient High-Speed VLSI Adaptive Filter Architectures", Proceedings of the IEEE International Conference on Communications, Seattle, June 1987, invited talk

1988

1. K.K. Parhi, and D.G. Messerschmitt, "Pipelined VLSI Recursive Filter Architectures using Scattered Look-Ahead and Decomposition", Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing, April 1988, pp. 2120-2123
2. K.K. Parhi, and D.G. Messerschmitt, "Two-Dimensional Recursive Digital Filtering: Pipelining, One- and Two-Dimensional Block Processing",  IEEE International Symposium on Circuits and Systems, Helsinki, June 1988, pp. 1521-1524

1989

1. R. Ramaswami, and K.K. Parhi, "Distributed Scheduling of Broadcasts in a Radio Network", Proceedings of the 1989 IEEE Infocom, April 1989, Ottawa
2. K.K. Parhi, and D.G. Messerschmitt, "Rate-Optimal Fully-Static Multiprocessor Scheduling of Data-Flow Signal Processing Programs", IEEE International Symposium on Circuits and Systems, Oregon, May 1989, pp. 1923-1928
3. K.K. Parhi, "Look-Ahead in Dynamic Programming and Quantizer Loops", IEEE International Symposium on Circuits and Systems, Oregon, May 1989, (invited talk), pp. 1382-1387
4. K.K. Parhi, "Nibble-Serial Arithmetic Processor Designs via Unfolding", IEEE ISCAS 1989 (invited talk), pp. 635-640
5. K.K. Parhi and D.G. Messerschmitt, "Fully-Static Rate-Optimal Scheduling of Iterative Data-Flow Programs via Optimum Unfolding", Proc. of the 1989 International Conference on Parallel Processing, August 1989, pp. I:209-216, St. Charles (Illinois)

1990

1. K.K. Parhi, "High-Speed Architectures for Dynamic Programming Problems", in Proc. of 1990 IEEE International Conference on Acoustics, Speech, and Signal Processing , April 1990, Albuquerque, pp. 1041-1044
2. K. K. Parhi, G.S. Munson, and L.Q. Pham, "Quantization Effects in High-Speed Pipelined Recursive Filters", in Proc. of IEEE International Conference on Acoustics, Speech, and Signal Processing , April 1990, Albuquerque, pp. 1743-1746
3. K.K. Parhi, "High-Speed Architectures for Algorithms with Quantizer Loops", in Proc. of the IEEE International Symposium on Circuits and Systems , May 1990, New Orleans ( invited talk ), pp. 2357-2360
4. K.K. Parhi, and C.Y. Wang, "Digit-Serial DSP Architectures", Proceedings of the Third Conference on Application-Specific Array Processors , September 1990, Princeton, IEEE Computer Society Press, pp. 341-351
5. C.Y. Wang, and K.K. Parhi, "Automatic Generation of Control Circuits in Pipelined DSP Architectures", in Proceedings of the IEEE International Conference on Computer Design , September 1990, Cambridge (MA), pp. 324-327
6. C.-Y. Wang, and K.K. Parhi, "Dedicated DSP Architecture Synthesis using the MARS Design System", Proc. of the 1991 IEEE Int. Conf. on Acoustics, Speech, and Signal Processing , pp. 1253-1256, Toronto, May 1991

1991

1. K.K. Parhi, and J.-S. Lee, "Register Allocation for Design of Data Converters", Proc. of the 1991 IEEE Int. Conf. on Acoustics, Speech, and Signal Processing , pp. 1133-1136, Toronto, May 1991
2. F.H. Wu, K.K. Parhi, and K. Ganesan, "Neural Network Vector Quantizer Design using Sequential and Parallel Learning Techniques", Proc. of the 1991 IEEE Int. Conf. on Acoustics, Speech, and Signal Processing , pp. 637-640, Toronto, May 1991
3. L.E. Lucke, A.P. Brown, and K.K. Parhi, "Unfolding and Retiming for High-Level Synthesis", in Proc. of 1991 IEEE International Symposium on Circuits and Systems , June 1991, Singapore ( invited talk ), pp. 2351-2354
4. K.K. Parhi, "Register Minimization in DSP Data Format Converters", in Proc. of 1991 IEEE International Symposium on Circuits and Systems , June 1991, Singapore ( invited talk ), pp. 2367-2370
5. K.K. Parhi, "Register Minimization in DSP Data Format Converters",  in Proc. of 1991 IEEE International Symposium on Circuits and Systems , June 1991, Singapore ( invited talk ), pp. 2367-2370
6. H.R. Srinivas, and K.K. Parhi, "High-Speed VLSI Arithmetic Processor Architectures Using Hybrid Number Representation", in Proc. of the 1991 IEEE Int. Conf. on Computer Design , October 1991, Cambridge, Massachusetts, pp. 564-571
7. K.K. Parhi, "High-Speed Huffman Decoder Architectures", in Proc. of Twenty-Fifth Annual Asilomar Conference on Signals, Systems, and Computers , Nov. 4-6, 1991, Pacific Grove (CA), pp. 64-68
8. N.R. Shanbhag, and K.K. Parhi, "A Pipelined LMS Adaptive Filter Architecture", in Proc. of Twenty-Fifth Annual Asilomar Conference on Signals, Systems, and Computers , Nov. 4-6, 1991, Pacific Grove (CA), pp. 668-672
9. J-G. Chung, and K.K. Parhi, "Design of Pipelined Lattice IIR Digital Filters", in Proc. of Twenty-Fifth Annual Asilomar Conference on Signals, Systems, and Computers , Nov. 4-6, 1991, Pacific Grove (CA), pp. 1021-1025

1992

1. L.E. Lucke, and K.K. Parhi, "Parallel Structures For Rank-Order and Stack Filters", in Proc. of the 1992 IEEE Int. Conf. on Acoustics, Speech, and Signal Processing , March 1992 (San Francisco), pp. V-645-648
2. K.J. Raghunath, and K.K. Parhi, "Parallel Adaptive DFE Algorithms", in Proc. of the 1992 IEEE Int. Conf. on Acoustics, Speech, and Signal Processing , March 1992 (San Francisco), pp. IV-353-356
3. L.E. Lucke, and K.K. Parhi, "A New VLSI Architecture for Rank-Order and Stack Filters", in Proc. of the IEEE International Symposium on Circuits and Systems , San Diego, May 1992, pp. 101-104
4. C.-Y. Wang, and K.K. Parhi, "High-Level DSP Synthesis using Mars System", in Proc. of the IEEE International Symposium on Circuits and Systems , San Diego, May 1992 ( invited talk ), pp. 164-167
5. N.R. Shanbhag, and K.K. Parhi, "A High-Speed Architecture for ADPCM Coder and Decoder", in Proc. of the IEEE International Symposium on Circuits and Systems , San Diego, May 1992, pp. 1499-1502
6. N.R. Shanbhag, and K.K. Parhi, "A Pipelined Adaptive Lattice Filter Architecture", in Proc. of the IEEE International Symposium on Circuits and Systems , San Diego, May 1992, pp. 2196-2199
7. N.R. Shanbhag, and K.K. Parhi, "A Pipelined Adaptive Lattice Filter Architecture", Proc. of the 1992 European Signal Processing Conference , August 24-28, 1992, Brussels (Belgium), pp. 1057-1060
8. N.R. Shanbhag, and K.K. Parhi, "A Pipelined Adaptive Differential Vector Quantizer for Real-Time Video Compression", Proc. of the IEEE Workshop on Visual Signal Processing and Communications , September 1992, Raleigh, North Carolina, pp. 9-14
9. K.K. Parhi, "Impact of Architecture Choices on DSP Circuits", Proc. of the IEEE TENCON: Region 10 Int. Conference on Computers, Communications, and Automation , Nov. 9-13, 1992, Melbourne, Australia, pp. 784-788 ( invited talk )

1993

1. L.E. Lucke, and K.K. Parhi, "VLSI Structures for Weighted Order Statistics Filters", in Proc. of IEEE Winter Workshop on Nonlinear Digital Signal Processing , Tampere, Finland, January 17-20, 1993, pp. 5.2.2.1-5.2.2.5
2. G. Shrimali, and K.K. Parhi, "Fast Arithmetic Decoder Architectures", Proceedings of Sixth SIAM Conference on Parallel Processing for Scientific Computing , March 22-24, 1993, Norfolk, VA, pp. 1025-1032
3. L.E. Lucke, and K.K. Parhi, "Block Processing for Rank-Order Filtering using the Rank-Order State Machine Architecture", in Proc. of the 1993 IEEE Int. Conf. on Acoustics, Speech, and Signal Processing , April 1993, Minneapolis (MN), pp. I-357-360
4. G. Shrimali, and K.K. Parhi, "Fast Arithmetic Coder Architectures", in Proc. of the 1993 IEEE Int. Conf. on Acoustics, Speech, and Signal Processing , April 1993, Minneapolis (MN), pp. I-361-364
5. T.C. Denk, K.K. Parhi, and V. Cherkassky, "Combining Neural Network and the Wavelet Transform for Image Compression", in Proc. of the 1993 IEEE Int. Conf. on Acoustics, Speech, and Signal Processing , April 1993, Minneapolis (MN), pp. I-637-640
6. J.-G. Chung, and K.K. Parhi, "The Scaled Normalized Lattice Digital Filter", Proc. of the 1993 IEEE Int. Symp. on Circuits and Systems , May 1993, Chicago, pp. 483-486
7. N.R. Shanbhag, and K.K. Parhi, "Roundoff Error Analysis of the Pipelined ADPCM Coder", Proc. of the 1993 IEEE Int. Symp. on Circuits and Systems , May 1993, Chicago, pp. 886-889
8. C.-Y. Wang, and K.K. Parhi, "Loop List Scheduler for DSP Algorithms under Resource Constraints", Proc. of the 1993 IEEE Int. Symp. on Circuits and Systems , May 1993, Chicago, pp. 1662-1665
9. K.K. Parhi, and T. Nishitani, "Folded VLSI Architectures for Discrete Wavelet Transforms", Proc. of the 1993 IEEE Int. Symp. on Circuits and Systems , May 1993, Chicago, pp. 1734-1737
10. N.R. Shanbhag, and K.K. Parhi, "A Pipelined Adaptive Differential Vector Quantizer for Low-Power Speech Compression", Proc. of the 1993 IEEE Int. Symp. on Circuits and Systems , May 1993, Chicago, pp. 1956-1958
11. K.J. Raghunath, and K.K. Parhi, "High-Speed RLS using Scaled Tangent Rotation (STAR)", Proc. of the 1993 IEEE Int. Symp. on Circuits and Systems , May 1993, Chicago, pp. 1959-1962
12. L.E. Lucke, and K.K. Parhi, "Generalized ILP Scheduling and Allocation for High-Level DSP Synthesis", in Proc. of IEEE Custom Integrated Circuit Conference , May 9-12, 1993, San Diego, CA, pp. 5.4.1-5.4.4
13. G. Shrimali, and K.K. Parhi, "High-Speed Arithmetic Decoder Architectures", in Proc. of the IEEE Int. Conference on Communications , May 23-26, 1993, Geneva (Switzerland), pp. 222-226
14. K.K. Parhi, "Algorithms and Architectures for High-Speed or Low-Power Digital Signal Processing", Proceedings of the 4th International Conference on Advances in Communications and Control (COMCON 4) , Rhodes, Greece, June 14-18, 1993, pp. 259-270
15. K.J. Raghunath, and K.K. Parhi, "Pipelined Implementation of High Speed STAR-RLS Adaptive Filters", Proc. of the SPIE Advanced Signal Processing Algorithms, Architectures, and Implementations IV, 1993 Int. Symp. on Optical Appl. Sci. and Eng. , Vol. 2027, July 11-16, 1993, San Diego (CA), pp. 122-133
16. N.R. Shanbhag, and K.K. Parhi, "Pipelined Adaptive DFE Architectures", Proc. of the SPIE Advanced Signal Processing Algorithms, Architectures, and Implementations IV, 1993 Int. Symp. on Optical Appl. Sci. and Eng. , Vol. 2027, July 11-16, 1993, San Diego (CA), pp. 134-145
17. N.R. Shanbhag, and K.K. Parhi, "Pipelined Adaptive Quantizers using Relaxed Look-Ahead", in Proc. of the 1993 IEEE Workshop on VLSI in Communications , Sept. 15-17, 1993, Stanford Sierra Camp, Lake Tahoe, California
18. H.R. Srinivas, B. Vinnakota, and K.K. Parhi, "A C-Testable Carry-Free Divider", Proceedings of the 1993 IEEE Int. Conf. on Computer Design , October 3-6, 1993, Cambridge, MA, pp. 206-213
19. L.E. Lucke, and K.K. Parhi, "Parallel Processing Architectures for Rank-Order and Stack Filters", Proc. of the 1993 Int. Conf. on Application Specific Array Processors , Oct. 1993, Venice (Italy), pp. 65-76
20. N.R. Shanbhag, and K.K. Parhi, "A Pipelined Kalman Filter Architecture", Proc. of the 27th Annual Asilomar Conf. on Signals, Systems, and Computers , Nov. 1-3, 1993, Pacific Grove (CA), pp. 1225-1229
21. J.-G. Chung, and K.K. Parhi, "Pipelining of Orthogonal Double-Rotation Digital Lattice Filters", Proc. of the 27th Annual Asilomar Conf. on Signals, Systems, and Computers , Nov. 1-3, 1993, Pacific Grove (CA), pp. 1613-1617

1994

1. K.K. Parhi, "Calculation of Minimum Number of Registers in Arbitrary Life Time Chart", Proc. of the Seventh Int. Conf. on VLSI Design , IEEE Computer Society Press, pp. 83-86, Calcutta, India, January 5-8, 1994
2. K.J. Raghunath, and K.K. Parhi, "Fixed and Floating Point Error Analysis of QRD-RLS and STAR-RLS Adaptive Filters", Proc. of the 1994 IEEE Int. Conf. on Acoustics, Speech, and Signal Processing , pp. III-81-III-84, April 19-22, 1994, Adelaide, Australia
3. T.C. Denk, and K.K. Parhi, "Calculation of Minimum Number of Registers in 2-D Discrete Wavelet Transforms using Lapped Block Processing", Proc. of 1994 IEEE Int. Symp. on Circuits and Systems , pp. 3.77-3.80, May 30 - June 2, 1994, London
4. H.R. Srinivas, and K.K. Parhi, "A Fast Radix-4 Division Algorithm", Proc. of 1994 IEEE Int. Symp. on Circuits and Systems , pp. 4.311-4.314, May 30 - June 2, 1994, London
5. K.K. Parhi and T.C. Denk, "VLSI Discrete Wavelet Transform Architectures", in Proc. of the 1st ARPA RASSP Conference , pp. 154-170, Aug. 15-18, 1994, Arlington (VA)
6. T.C. Denk, and K.K. Parhi, "Architectures for Lattice Structure Based Orthonormal Discrete Wavelet Transforms", Proc. of the 1994 Int. Conf. on Application Specific Array Processors , pp. 259-270, San Francisco, August 1994
7. H.R. Srinivas and K.K. Parhi, "Computer Arithmetic Architectures with Redundant Number System", Proc. of the 28th Asilomar Conf. on Signals, Systems, and Computers , pp. 182-186, Oct. 31 - Nov. 2, 1994, Pacific Grove, CA ( Invited Talk )
8. K.K. Parhi, "VLSI Digital Signal Processing Education", Proc. of the 28th Asilomar Conf. on Signals, Systems, and Computers , pp. 1303-1308, Oct. 31 - Nov. 2, 1994, Pacific Grove, CA ( Invited Talk )
9. K. Ito, L.E. Lucke and K.K. Parhi, "Module Selection and Data Format Conversion for Cost-Optimal DSP Synthesis", Proc. of the IEEE/ACM Int. Conf. on Computer Aided Design , pp. 322-329, Nov. 6-10, 1994, San Jose (CA)
10. K. Ito and K.K. Parhi, "Determining the Iteration Bound of Data-Flow Graphs", Proc. of the IEEE Asia-Pacific Conference on Circuits and Systems , pp. 163-168, Dec. 5-8, 1994, Grand Hotel, Taipei

1995

1. W. Amendola, Jr., H.R. Srinivas, and K.K. Parhi, "A 16-Bit X 16-Bit 1.2 Micron CMOS Multiplier Chip with Low Latency Vector Merging", Proc. of the 8th Int. Conf. on VLSI Design , IEEE Computer Society Press, pp. 398-402, Jan. 4-7, 1995, New Delhi, India
2. J.-G. Chung and K.K. Parhi, "Synthesis and Pipelining of Ladder Wave Digital Filters in Digital Domain", in Proc. of the 1995 IEEE Int. Symp. on Circuits and Systems , pp. 77-80, Seattle, May 1995
3. D. Pearson and K.K. Parhi, "Low-Power FIR Digital Filter Architectures", in Proc. of the 1995 IEEE Int. Symp. on Circuits and Systems , pp. 231-234, Seattle, May 1995
4. B. Fu and K.K. Parhi, "Generalized Multiplication Free Arithmetic Codes", in Proc. of the 1995 IEEE Int. Symp. on Circuits and Systems , pp. 437-440, Seattle, May 1995
5. B. Fu and K.K. Parhi, "Two VLSI Design Advances in Arithmetic Coding", in Proc. of the 1995 IEEE Int. Symp. on Circuits and Systems , pp. 1440-1443, Seattle, May 1995
6. S. Jain and K.K. Parhi, "A Low-Latency Standard Basis GF($2^m$) Multiplier", in Proc. of the 1995 IEEE Int. Conf. on Acoustics, Speech and Signal Processing , pp. 2747-2750, May 1995, Detroit (MI)
7. K.J. Raghunath and K.K. Parhi, "A 100 MHz RLS Adaptive Filter Chip", in Proc. of the 1995 IEEE Int. Conf. on Acoustics, Speech and Signal Processing , pp. 3187-3190, May 1995, Detroit (MI)
8. K.K. Parhi, "Trading off Concurrency for Low-Power in Linear and Nonlinear Computations", in Proc. of 1995 IEEE Workshop on Nonlinear Signal Processing , June 1995, pp. 895-898, Thessaloniki, Greece
9. H.R. Srinivas and K.K. Parhi, "A Floating Point Radix 2 Shared Division/Square Root Chip", Proc. of the 1995 IEEE Int. Conf. on Computer Design , pp. 472-478, October 1995, Austin
10. C.-Y. Wang and K.K. Parhi, "MARS: A High-Level DSP Synthesis Tool  Integrated within the Mentor Graphics Environment", in Proc. of Mentor Graphics Users' Group Annual Conference , October 22-27, 1995, Portland
11. Y.N. Chang, C.Y. Wang and K.K. Parhi, "High-Level DSP Synthesis with Heterogeneous Functional Units using the MARS-II System", Proc. of the 1995 Asilomar Conf. on Signals, Systems and Computers, pp. 109-116, Pacific Grove (CA), November 1995 ( invited talk )

1996

1. Y.-N. Chang, C.Y. Wang, and K.K. Parhi, "Loop List Scheduling for Heterogeneous Functional Units", Proc. of Sixth Great Lakes Symp. on VLSI , pp. 2-7, March 1996, Ames (Iowa)
2. S.K. Jain and K.K. Parhi, "Efficient Standard Basis Reed-Solomon Encoder", in Proc. of 1996 IEEE Int. Conf. on Acoustics, Speech and Signal Processing , pp. 3287-3290, May 1996, Atlanta
3. T.C. Denk, M. Majumdar and K.K. Parhi, "Two-Dimensional Retiming with Low Memory Requirements", in Proc. of 1996 IEEE Int. Conf. on Acoustics, Speech and Signal Processing , pp. 3330-3333, May 1996, Atlanta
4. J. Satyanarayana and K.K. Parhi, "A Hierarchical Approach to Transistor Level Power Estimation of Arithmetic Units", in Proc. of 1996 IEEE Int. Conf. on Acoustics, Speech and Signal Processing , pp. 3338-3341, May 1996, Atlanta
5. Y. Li and K.K. Parhi, "STAR RLS Lattice Adaptive Filters", in Proc. of 1996 IEEE Int. Symp. on Circuits and Systems , pp. II: 389-392, May 1996, Atlanta
6. A. Shalash and K.K. Parhi, "Comparison of Discrete Multitone and Carrierless AM/PM Techniques for Line Equalization", in Proc. of 1996 IEEE Int. Symp. on Circuits and Systems , pp. II: 560-563, May 1996, Atlanta
7. L. Montalvo and K.K. Parhi, "Radix-2 Over-Redundant Digit-Set Convereters", in Proc. of 1996 IEEE Int. Symp. on Circuits and Systems , pp. 81-84, May 1996, Atlanta
8. M. Majumdar and K.K. Parhi, "Synthesis of Low-Area Data Format Converters", Proc. of 1996 IEEE Int. Symp. on Circuits and Systems , pp. 145-148, May 1996, Atlanta
9. T.C. Denk and K.K. Parhi, "A Unified Framework for Characterizing Retiming and Scheduling Solutions", in Proc. of 1996 IEEE Int. Symp. on Circuits and Systems , pp. 568-571, May 1996, Atlanta
10. J. Satyanarayana and K.K. Parhi, "HEAT: Hierarchical Energy Analysis Tool", Proc. of ACM\/IEEE Design Automation Conference , Las Vegas, pp. 9-14, June 3-7, 1996
11. L.L. Song and K.K. Parhi, "Efficient Finite Field Serial/Parallel Multiplication", Proc. of the 1996 Int. Conf. on Applications-specific Systems, Architectures, and Processors , pp. 72-82, Chicago, August 1996
12. D.A. Parker and K.K. Parhi, "Low Area/Power Parallel FIR Digital Filters", Proc. of the 1996 Int. Conf. on Applications-specific Systems, Architectures, and Processors , pp. 93-111, Chicago, August 1996
13. J.H. Satyanarayana, K.K. Parhi, L.L. Song and Y.N. Chang "Systematic Analysis of Bounds on Power Consumption in Pipelined and Non-pipelined Multipliers", Proc. of 1996 IEEE Int. Conf. on Computer Design , pp. 492-499, October 1996, Austin (Texas)
14. C. Xu, C.-Y. Wang and K.K. Parhi, "Order-Configurable Programmable Power Efficient FIR Filters", Proc. of 3rd Int. Workshop on Image and Signal Processing , pp. 535-538, November 1996, UMIST (UK) ( Invited Talk )
15. L. Montalvo and K.K. Parhi, "Estimation of Average Energy Consumption of Ripple Carry Adder Based on Average Length Carry Chains", Proc. of 1996 Design of Integrated Circuits and Systems Conf. (DCIS) , pp. 11-16, Barcelona (Spain), Nov. 1996
16. J.P. Ma, K.K. Parhi, and E.F. Deprettere, "Pipelining of Cordic Based IIR Digital Filters", Proc. of ProRISC/IEEE Workshop , Mierlo, The Netherlands, Nov. 1996
17. C. Xu, C.-Y. Wang and K.K. Parhi, "Order-Configurable Programmable Power Efficient FIR Filters", Proc. of Int. Conf. on High Performance Computing , pp. 357-361, Trivandrum (India), December 1996 ( Invited Talk )

1997

1. J.P. Ma, K.K. Parhi and E.F. Deprettere, "Pipelining of Cordic Based IIR Digital Filters", Proc. of IEEE Int. Conf. on Acoustics, Speech and Signal Processing , pp. 643-646, Munich, April 1997
2. L. Song and K.K. Parhi, "Low-Area Dual-Basis Divider Over $GF(2^M)$", Proc. of IEEE Int. Conf. on Acoustics, Speech and Signal Processing , pp. 627-530, Munich, April 1997
3. A. Shalash and K.K. Parhi, "Three-Dimensional Carrierless AM/PM Line Code for Unshielded Twisted Pair Cables", Proc. of IEEE Int. Symp. on Circuits and Systems , pp. 2136-2139, Hong Kong, June 1997 ( Invited Talk )
4. Y.N. Chang, J. Satyanarayana and K.K. Parhi, "Low-Power Digit-Serial Architectures", Proc. of IEEE Int. Symp. on Circuits and Systems , pp. 2164-2167, Hong Kong, June 1997 ( Invited Talk )
5. H. Kim, J.-G. Chung and K.K. Parhi, "Low-Noise Implementation Technique for Pipelined Filters with Crowded Poles", Proc. of IEEE Int. Symp. on Circuits and Systems , pp. 2196-2199, Hong Kong, June 1997
6. T.T. Vu, P.C. Nguyen,L.T. Vu, C.H. Nguyen, M.D. Bui, A.C. Nguyen, J.N.C. Vu, R. Harjani, L.L. Kinney, K.K. Parhi, D.L. Polla, R. Schaumann, P.J. Schiller and M.S. Shur, "Microsensors Fabricated in Gallium Arsenide", Proc. of Technology 2007 (NASA Tech Briefs, Federal Laboratory Consortium, and Technology Utilization Foundation) , Sept. 22-24, 1997, Boston, MA
7. V. Sundararajan, M.E. Zervakis and K.K. Parhi, "Area/Power Efficient Implementation of a Wavelet Domain Robust Image Denoising System", Proc. of IEEE Workshop on Non-Linear Signal Processing , Michigan, September 1997
8. L. Song, K.K. Parhi, I. Kuroda and T. Nishitani, "Heterogeneous Digit-Serial Finite Field Multipliers and Low-Energy Reed-Solomon Codecs", Proc. of 35th Annual Allerton Conference on Communication, Control, and Computing , Illinois, Sept. 29 - Oct. 1, 1997 Invited Talk
9. Y.-N. Chang, J.H. Satyanarayana, and K.K. Parhi, "Design and Implementation of Low-Power Digit-Serial Multipliers", Proc. of IEEE Conf. on Computer Design , pp. 186-195, Austin, October 12-15, 1997
10. K.K. Parhi, "Fast Low-Energy VLSI Binary Addition", Proc. of IEEE Conf. on Computer Design , pp. 676-684, Austin, October 12-15, 1997
11. K.K. Parhi, "Low-Power Multimedia DSP Systems", Proc. of 1997 Int. Conf. on VLSI and CAD (ICVC) , pp. 10-17, Seoul, Korea, Oct. 13-15, 1997, Plenary Talk
12. M.E. Zervakis, V. Sundararajan and K.K. Parhi, "A Wavelet-Domain Algorithm for Denoising in the Presence of Noise Outliers", Proc. of IEEE Int. Conf. on Image Processing , pp. I-632-I-635, Santa Barbara, October 26-29, 1997
13. W. Freking and K.K. Parhi, "Low-Power Digital Filters using Residue Arithmetic", Proc. of 1997 Asilomar Conf. on Signals, Systems and Computers , pp. 739-743, November 1997 Invited Talk
14. J. Ma, E.F. Deprettere and K.K. Parhi, "Pipelined Cordic Based QRD-RLS Adaptive Filtering Using Matrix Look-Ahead" Proc. of 1997 IEEE Workshop on Signal Processing Systems: Design and Implementation , pp. 131-140, Leicester, U.K., Nov. 1997
15. K.K. Parhi, "Fast VLSI Binary Addition", Proc. of 1997 IEEE Workshop on Signal Processing Systems: Design and Implementation , pp. 232-241, Leicester, U.K., Nov. 1997
16. L. Song and K.K. Parhi, "Optimum Primitive Polynominals for Low Area and Low Power Finite Field Semi-Systolic Multipliers", Proc. of 1997 IEEE Workshop on Signal Processing Systems: Design and Implementation , pp. 375-384, Leicester, U.K., Nov. 1997

1998

1. T.T. Vu, P.C. Nguyen, L.T. Vu, C.H. Nguyen, M.D. Bui, A.C. Nguyen, J.N.C. Vu, R. Harjani, K.K. Parhi, D.L. Polla, R. Schaumann, P.J. Schiller and M.S. Shur, "Gallium Arsenide Based Microsensor Systems", Proc. of Government Microcircuit Applications Conference , March 16-19, 1998, Arlington, Virginia
2. J. Ma, K.K. Parhi, and E.F. Deprettere, "Pipelined Cordic Based QRD-MVDR Adaptive Beamforming", in Proc. of IEEE Int. Conf. on Acoustics, Speech and Signal Processing , pp. 3025-3028, May 1998, Seattle
3. L. Song, K.K. Parhi, I. Kuroda, and T. Nishitani, "Low-energy Heterogeneous Digit-Serial Reed-Solomon Codecs", in Proc. of IEEE Int. Conf. on Acoustics, Speech and Signal Processing , pp. 3049-3052, May 1998, Seattle
4. V. Sundararajan and K.K. Parhi, "Synthesis of Folded, Pipelined Architectures for Multi-Dimensional Multirate Systems", in Proc. of IEEE Int. Conf. on Acoustics, Speech and Signal Processing , pp. 3089-3092, May 1998, Seattle
5. L. Song, K.K. Parhi, I. Kuroda and T. Nishitani, "Low-Energy Programmable Finite Field Datapath Architectures", Proc. of IEEE Int. Symp. on Circuits and Systems , pp. II-406-II-409, Monterey, May 31 - June 3, 1998
6. J. Ma, K.K. Parhi, and E.F. Deprettere, "High-Speed Cordic Based Parallel Weight Extraction For QRD-RLS Adaptive Filtering", Proc. of IEEE Int. Symp. on Circuits and Systems , pp. V-245-V-248, Monterey, May 31 - June 3, 1998
7. V. Sundararajan and K.K. Parhi, "Synthesis of Folded Multi-Dimensional DSP Systems", Proc. of IEEE Int. Symp. on Circuits and Systems , pp. II-433-II-436, Monterey, May 31 - June 3, 1998
8. R. Freking and K.K. Parhi, "Theretical Estimation of Power Consumption in Binary Adders", Proc. of IEEE Int. Symp. on Circuits and Systems , pp. II-453-II-457, Monterey, May 31 - June 3, 1998
9. J.-G. Chung, Y.-B. Kim, H.-J. Jeong, and K.K. Parhi, "Efficient Parallel FIR Filter Implementations using Frequency Spectrum Characteristics", Proc. of IEEE Int. Symp. on Circuits and Systems , pp. V-354-V-358, Monterey, May 31 - June 3, 1998
10. A. Shalash and K.K. Parhi, "Three-Dimensional Equalization for the 3-D QAM System with Strength Reduction", Proc. of IEEE Int. Symp. on Circuits and Systems , pp. IV-453-IV-456, Monterey, May 31 - June 3, 1998
11. M. Kuhlmann and K.K. Parhi, "Power Comparison of SRT and NST Dividers", Proc. of the SPIE Advanced Signal Processing Algorithms, Architectures, and Implementations VIII, 1998 Int. Symp. on Optical Sci., Eng. and Instrumentation , July 19-24, 1998, San Diego (CA)
12. J. Ma, K.K. Parhi, G.J. Hekstra, and E.F. Deprettere, "Efficient implementations of Cordic-based IIR digital filters using fast orthonormal micro-rotations, Proc. of the SPIE Advanced Signal Processing Algorithms, Architectures, and Implementations VIII, 1998 Int. Symp. on Optical Sci., Eng. and Instrumentation , July 19-24, 1998, San Diego (CA)
13. J. Ma and K.K. Parhi, "High-Speed VLSI State-Space Orthogonal IIR Digital Filters Using Matrix Lookahead", Proc. of 1998 IEEE Workshop on Signal Processing Systems: Design and Implementations (SiPS) , pp. 417-426, Oct. 8-10, 1998, Boston
14. L. Song and K.K. Parhi, "Scheduling Stragegies for Low-Energy Programmable Digit-Serial Reed-Solomon Codecs", Proc. of 1998 IEEE Workshop on Signal Processing Systems: Design and Implementations (SiPS) , pp. 275-284, Oct. 8-10, 1998, Boston
15. M. Kuhlmann and K.K. Parhi, "Fast Low-Power Shared Division and Sqaure-Root Architecture", Proc. of 1998 IEEE Int. Conf. on Computer Design , pp. 128-135, Austin, Oct. 1998
16. A. Karandikar and K.K. Parhi, "Low-Power SRAM Design Using Hierarchical Divided Bit-Line Approach", Proc. of 1998 IEEE Int. Conf. on Computer Design , pp. 82-88, Austin, Oct. 1998
17. Y.N. Chang and K.K. Parhi, "High-Performance Digit-Serial Complex-Number Multiplier-Accumulator", Proc. of 1998 IEEE Int. Conf. on Computer Design , pp. 211-213, Austin, Oct. 1998
18. A. Shalash and K.K. Parhi, "Power Efficient FIR Folding Transformation for Wireline Digital Communications", Proc. of 1998 Asilomar Conf. on Signals, Systems and Computers , Nov. 1-4, 1998, Pacific Grove (CA)
19. M. Kuhlmann and K.K. Parhi, "Power Comparison of Flow-Graph and Distributed Arithmetic Based DCTs", Proc. of 1998 Asilomar Conf. on Signals, Systems and Computers , Nov. 1-4, 1998, Pacific Grove (CA)
20. T.C. Denk and K.K. Parhi, Systolic VLSI Architectures for 1-D Discrete Wavelet Transforms", Proc. of 1998 Asilomar Conf. on Signals, Systems and Computers , Nov. 1-4, 1998, Pacific Grove (CA)
21. H. Suzuki, Y.N. Chang and K.K. Parhi, "Performance Tradeoffs in Digit-Serial DSP Systems", Proc. of 1998 Asilomar Conf. on Signals, Systems and Computers , Nov. 1-4, 1998, Pacific Grove (CA)

1999

1. J.H. Satyanarayana and K.K. Parhi, "Theoretical Analysis of Word-Level Switching Activity in the Presence of Glitching and Correlation", Proc. of 9th Great Lakes Symp. on VLSI , March 1999, Ann Arbor, MI
2. V. Sundararajan and K.K. Parhi, "Low-Power Gate Resizing of Combinational Circuits by Buffer-Redistribution", 20th Anniversary Conferene on Advanced Research in VLSI , March 1999
3. H. Suzuki, Y.N. Chang and K.K. Parhi, "Low-Power Bit-Serial Viterbi Decoder for Next Generation Wide-Band CDMA Systems", Proc. of 1999 IEEE Int. Conf. on Acoustics, Speech and Signal Processing , Phoenix, March 1999
4. R.A. Freking and K.K. Parhi, "An Unrestrictedly Parallel Scheme for Ultra-High-Rate Reprogrammable Huffman Coding", Proc. of 1999 IEEE Int. Conf. on Acoustics, Speech and Signal Processing , Phoenix, March 1999
5. H. Suzuki, Y.N. Chang and K.K. Parhi, "256 States Low-Power Bit-Serial Viterbi Decoder for Next Generation Wireless Applications", Proc. of 1999 IEEE Customs Integrated Circuits (CICC) Conference , San Diego, May 1999
6. W.L. Freking and K.K. Parhi, "Parallel Modular Multiplication with Application to VLSI RSA Implementation", Proc. of 1999 IEEE Int. Symp. on Circuits and Systems , Orlando, June 1999
7. J. Ma, K.K. Parhi and E.F. Deprettere, "Derivation of Parallel and Pipelined Orthogonal Filter Architectures via Algorithm Transformations", Proc. of 1999 IEEE Int. Symp. on Circuits and Systems , Orlando, June 1999
8. L. Song and K.K. Parhi, "Low-Energy Software Reed-Solomon Codecs Using Specialized Finite Field Datapath and Division-Free Berlekamp-Massey Algorithm", Proc. of 1999 IEEE Int. Symp. on Circuits and Systems , Orlando, June 1999
9. L. Song and K.K. Parhi, "Low-Complexity Modified Mastrovito Multipliers over Finite Fields GF(2**m)", Proc. of 1999 IEEE Int. Symp. on Circuits and Systems , Orlando, June 1999
10. S. Summerfield, Z. Wang and K.K. Parhi, "Area-Power-Time Efficient Pipeline-Interleaved Architectures for Wave Digital Filters", Proc. of 1999 IEEE Int. Symp. on Circuits and Systems , Orlando, June 1999
11. Z. Chi, J. Ma and K.K. Parhi, "Pipelined QR Decomposition Based Least Square Lattice Adaptive Filter Architecture", Proc. of 1999 IEEE Int. Symp. on Circuits and Systems , Orlando, June 1999
12. V. Sundararajan and K.K. Parhi, "Synthesis of Low-Power CMOS VLSI Circuits using Dual Supply Voltages", Proc. of 1999 ACM Design Automation Conference , New Orleans, June 1999
13. A. Shalash and K.K. Parhi, "Orthogonality Division Multiple Access LTI Transmit Filters for ISI Channels", Proc. of 1999 IEEE Int. Conf. on Communications, Vancouver, BC, June 1999
14. V. Sundararajan and K.K. Parhi, "Low Power Synthesis of Dual Threshold Voltage CMOS VLSI Circuits" Proc. of 1999 IEEE Int. Symp. on Low Power Electronics and Design , San Diego, August 1999
15. W.L. Freking and K.K. Parhi, "A Unified Method for Iterative Computation of Modular Multiplication and Reduction Operations", Proc. of 1999 IEEE Int. Conf. on Computer Design , Austin, Oct. 1999
16. M. Kuhlmann, S. Sapatnekar and K.K. Parhi, "Efficient Crosstalk Estimation", Proc. of 1999 IEEE Int. Conf. on Computer Design , Austin, Oct. 1999
17. M. Kuhlmann and K.K. Parhi, "A High-Speed CORDIC Algorithm and Architecture for Digital Signal Processing Applications", Proc. of 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation , Taipei, Oct. 1999
18. Y.-N. Chang and K.K. Parhi, "Efficient FFT Implementation using Digit-Serial Arithmetic", Proc. of 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation , Taipei, Oct. 1999
19. Z. Wang, H. Suzuki and K.K. Parhi, "VLSI Implementation Issues of Turbo Decoder Design for Wireless Applications", Proc. of 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation , Taipei, Oct. 1999
20. D. Kumar and K.K. Parhi, "Performance Trade-off of DCT Architectures in Xilinx FPGAs", Proc. of 1999 Asilomar Conf. on Signals, Systems and Computers , Pacific Grove, CA, Oct. 24-27, 1999
21. W. Freking and K.K. Parhi, "Montgomery Multiplication and Exponentiation in the Resiude Number System", Proc. of 1999 Asilomar Conf. on Signals, Systems and Computers , Pacific Grove, CA, Oct. 24-27, 1999
22. M. Kuhlmann and K.K. Parhi, "A New CORDIC Rotation Method for Generalized Coordinate Systems", Proc. of 1999 Asilomar Conf. on Signals, Systems and Computers , Pacific Grove, CA, Oct. 24-27, 1999
23. J. Ma and K.K. Parhi, "An Algorithm Transformation Approach to CORDIC Based Parallel Singular Value Decomposition Architectures", Proc. of 1999 Asilomar Conf. on Signals, Systems and Computers , Pacific Grove, CA, Oct. 24-27, 1999
24. V. Sundararajan, S. S. Sapatnekar and K. K. Parhi, "MARSH: Min-Area Retiming with Setup and Hold Constraints", Proc. of 1999 IEEE/ACM International Conference on Computer-Aided Design , Nov. 1999

2000

1. V. Sundararajan and K.K. Parhi, "Synthesis of Low Power Folded Programmable Coefficient FIR Digital Filters", Proc. of 2000 IEEE Asia Pacific Design Automation Conference (ASP-DAC), pp. 153-156, Yokohama, Jan. 2000
2. V. Sundararajan and K.K. Parhi, "Data Transmission over a Bus with Peak-Limited Transition Activity", Proc. of 2000 IEEE Asia Pacific Design Automation Conference (ASP-DAC), pp. 221-224, Yokohama, Jan. 2000
3. V. Sundararajan and K.K. Parhi, "Reducing Bus Transition Activity by Limited Weight Coding with Codeword Slimming", Proc. of 2000 Great Lakes Symposium on VLSI, Chicago, IL, March 2000
4. B. Sahoo, M. Kuhlmann and K.K. Parhi, "A Low-Power Correlator", Proc. of 2000 Great Lakes Symposium on VLSI, Chicago, IL, March 2000
5. T. Sansaloni, J. Valls, and K.K. Parhi, "Digit-Serial Fixed-Coefficient Complex Number Multiplier Accumulator on FPGA", Proc. of 2000 IEEE Int. Symp. on Circuits and Systems, Geneva, May 2000
6. Z. Wang, H. Suzuki and K.K. Parhi, "Efficient Approaches to Improving Performance of VLSI SOVA-based Turbo Decoders", Proc. of 2000 IEEE Int. Symp. on Circuits and Systems, Geneva, May 2000
7. H. Suzuki, Z. Wang and K.K. Parhi, " A K=3 2 Mbps Low Power Turbo Decoder for 3rd Generation W-CDMA Systems", Proc. of 2000 IEEE Customs Integrated Circuits Conference, pp. 39-42, Orlando, May 2000
8. Z. Chi, Z. Wang and K.K. Parhi, "High-Throughput, Low-Energy FEC/ARQ Technique for Short Frame Turbo Codes", Proc. of 2000 IEEE Int. Conf. on Acoustics, Speech and Signal Processing, Vol. 5, pp. 2653-2656, Istanbul, June 2000
9. Z. Wang and K.K. Parhi, "Decoding Metrics and Their Applications in VLSI Turbo Decoders", Proc. of 2000 IEEE Int. Conf. on Acoustics, Speech and Signal Processing, Istanbul, June 2000
10. V. Sundararajan and K.K. Parhi, "A Novel Multiply Multiple Accumulator Component for Low Power PDSP Design", Proc. of 2000 IEEE Int. Conf. on Acoustics, Speech and Signal Processing, Vol. 6, pp. 3247-3250, Istanbul, June 2000
11. Y. Wang and K.K. Parhi, "Explicit Cook-Toom Algorithm for Linear Convolution", Proc. of 2000 IEEE Int. Conf. on Acoustics, Speech and Signal Processing, Vol. 6, pp. 3279-3282, Istanbul, June 2000
12. L. Gao, and K.K. Parhi, "Hierarchical Pipelining and Folding of QRD-RLS Adaptive Filters", Proc. of 2000 IEEE Int. Conf. on Acoustics, Speech and Signal Processing, Vol. 6, pp. 3283-3286, Istanbul, June 2000
13. V. Sundararajan, S.S. Sapatnekar and K.K. Parhi, "MINFLOTRANSIT: Min-Cost Flow Based Transistor Sizing Tool", Prof. of 2000 ACM/IEEE Design Automation Conference, pp. 649-654, Los Angeles, June 2000
14. W.L. Freking and K.K. Parhi, "Performance-Scalable Array Architectures for Modular Multiplication", Proc. of 2000 Applications-specific Systems, Architectures and Processors (ASAP) Conference, pp. 149-160, Boston, July 2000
15. L. Gao and K.K. Parhi, "Block-Update Parallel Processing QRD-RLS Algorithm for Throughput Improvement with Low-Power Consumption", Proc. of 2000 Applications-specific Systems, Architectures and Processors (ASAP) Conference, pp. 225-234, Boston, July 2000
16. T. Sansaloni, J. Valls and K.K. Parhi, "Digit-Serial Fixed Coefficient Complex Number Multiplier-Accumulator on FPGAs", Proc. of IEEE ASIC/SOC Conference, Sept. 2000
17. J. Valls, M. Kuhlmann and K.K. Parhi, "Efficient mapping of CORDIC algorithms on FPGA", Proc. of the 2000 IEEE Workshop on Signal Processing Systems (SiPS): Design and Implementation, pp. 336-345, Lafayette, LA, Oct. 2000
18. Z. Chi and K.K. Parhi, "High Speed Least Square Adaptive Filter Design Using ART and HAT", Proc. of the 2000 IEEE Workshop on Signal Processing Systems (SiPS): Design and Implementation, pp. 427-436, Lafayette, LA, Oct. 2000
19. W. Freking and K.K. Parhi, "Ring-Planarized Cylindrical Arrays with Application to Modular Multiplication", Proc. of the 2000 IEEE Workshop on Signal Processing Systems (SiPS): Design and Implementation, pp. 497-506, Lafayette, LA, Oct. 2000
20. T. Zhang and K.K. Parhi, "A Novel Systematic Design Approach of Mastrovito Multipliers over GF(2^m)", Proc. of the 2000 IEEE Workshop on Signal Processing Systems (SiPS): Design and Implementation, pp. 507-516, Lafayette, LA, Oct. 2000
21. R.A. Freking and K.K. Parhi, "Highly Parallel Arithmetic Coding", Proc. of 9th IEEE DSP Workshop, Hunt, Texas, Oct. 2000
22. Z. Chi, Z. Wang and K.K. Parhi, "Iterative Decoding of Space-Time Trellis Codes and Related Implementation Issues", Proc. of 2000 Asilomar Conference on Signals, Systems and Computers, pp. 562-566, Nov. 2000
23. R.A. Freking and K.K. Parhi, "Low-Memory, Fixed-Latency Huffman Encoder for Unbounded Codelength Codes", Proc. of 2000 Asilomar Conference on Signals, Systems and Computers, pp. 1031-1034, Nov. 2000
24. W. Freking and K.K. Parhi, "Modular Multiplication in the Residue Number System with Application to Massively-Parallel Public-Key Cryptography Systems" Proc. of 2000 Asilomar Conference on Signals, Systems and Computers, pp. 1339-1343, Nov. 2000
25. Y. Wang and K.K. Parhi, "Low-Power Binary Adders", Proc. of 2000 Asilomar Conference on Signals, Systems and Computers, pp. 1707-1712, Nov. 2000

2001

1. L. Gao and K.K. Parhi, "Models for Power Consumption and Power Grid Noise Due to Datapath Transition Activity ", Proc. of 2001 Great Lakes Symposium on VLSI, West Lafayette, IN, pp. 121-126, March 2001
2. I. Ben Dhaou, V. Sundararajan, H. Tenhunen and K.K. Parhi, "Energy Efficient Signaling in Deep Sub-Micron Technology", Proc. of 2001 International Symposium on Quality of Electronic Design (ISQED 2001), pp. 319-324, March 26-28, 2001, San Jose
3. I. Ben Dhaou, V. Sundararajan, H. Tenhunen, and K.K. Parhi, "Energy Efficient Signaling in Deep Submicron CMOS Technology", Proc. of 2001 IEEE Int. Symp. on Circuits and Systems, pp. 411-414, Sydney, May 2001
4. L. Gao and K.K. Parhi, "Custom VLSI Design of Efficient Low Latency and Low Power Finite Field Multiplier for Reed-Solomon Codec", Proc. of 2001 IEEE Int. Symp. on Circuits and Systems, pp. 574-577, Sydney, May 2001
5. Z. Chi, L. Song and K.K. Parhi, "A Study On The Performance, Complexity Tradeoffs Of Block Turbo Decoder Design", Proc. of 2001 IEEE Int. Symp. on Circuits and Systems, pp. 65-68, Sydney, May 2001
6. T. Zhang, Z. Wang and K.K. Parhi, "On Finite Precision Implementation of Low Density Parity Check Codes Decoder", Proc. of 2001 IEEE Int. Symp. on Circuits and Systems, pp. 202-205, Sydney, May 2001
7. Z. Wang, Z. Chi and K.K. Parhi, "Area-Efficient High Speed Decoding Schemes for Turbo/MAP Decoders", Proc. of 2001 IEEE Int. Conf. on Acoustics, Speech and Signal Processing, Salt Lake City, Utah, pp. 2633-2636, May 2001
8. Z. Chi and K.K. Parhi, "A Study on the Performance, Power Consumption Tradeoffs of Short Frame Turbo Decoder Design", Proc. of 2001 IEEE Int. Conf. on Acoustics, Speech and Signal Processing, Salt Lake City, Utah, pp. 2637-2640, May 2001
9. T. Zhang and K.K. Parhi, "A Class of Efficient-Encoding Generalized Low-Density Parity-Check Codes", Proc. of 2001 IEEE Int. Conf. on Acoustics, Speech and Signal Processing, Salt Lake City, Utah, pp. 2477-2480, May 2001
10. T. Zhang and K.K. Parhi, "VLSI implementation-oriented (3,k)-regular low-density parity-check codes", Proc. of 2001 IEEE Workshop on Signal Processing Systems, pp. 25-36, Antwerp, Belgium, Sept. 26-28, 2001
11. J.-G. Chung, S.-M. Kim, and K.K. Parhi, "Sign Extension Reduction by Look-Ahead Carry Computation", Proc. of 2001 Asilomar Conf. on Signals, Systems and Computers, Nov. 2001
12. Y. Wang and K.K. Parhi, "A Unified Adder Design", Proc. of 2001 Asilomar Conf. on Signals, Systems and Computers, Nov. 2001
13. T. Zhang and K.K. Parhi, "Joint Code and Decoder Design for Implementation Oriented (3,k)-Regular LDPC Codes", Proc. of 2001 Asilomar Conf. on Signals, Systems and Computers , Nov. 2001
14. K. Prasad and K.K. Parhi, "Low-Power 4-2 and 5-2 Compressors", Proc. of 2001 Asilomar Conf. on Signals, Systems and Computers , Nov. 2001
15. Y. Chen and K.K. Parhi, "A Very Low Complexity Block Turbo Decoder Composed of Extended Hamming Codes", Proc. of 2001 IEEE Globecom Conference, Vol. 1, pp. 171-175, San Antonio, Texas, Nov. 2001
16. T. Zhang and K.K. Parhi, "High-Performance Decoding of Generalized Low-Density Parity-Check Codes", Proc. of 2001 IEEE Globecom Conference, Vol. 1, pp. 181-185, San Antonio, Texas, Nov. 2001

2002

1. T. Zhang and K.K. Parhi, "On the High-Speed VLSI Implementation of Errors-and-Erasures Correct ing Reed-Solomon Decoders", Proc. of 2002 Great Lakes Symp. on VLSI, pp. 95-100, Binghamton, NY, April 2002
2. Y. Chen and K.K. Parhi, "A very low complexity soft decoding of space-time block codes", Proc. of IEEE Int. Conf. on Acoustics, Speech and Signal Processing, pp. 2693-2696, May 2002, Florida
3. Z. Chi and K.K. Parhi, "High Speed Algorithm and VLSI Architecture Design for Decoding BCH Product Codes", Proc. of IEEE Int. Conf. on Acoustics, Speech and Signal Processing, pp. 3089-3092, May 2002, Florida
4. S.-M. Kim, J.-G. Chung and K.K. Parhi, "Design of Low Error CSD Fixed-Width Multiplier", Proc. of 2002 IEEE Int. Symp. on Circuits and Systems, Vol. 1, pp. 69-72, Scottsdale, AZ, May 2002
5. G. Jung, J. Kim, G.E. Sobelman and K.K. Parhi, "High-Speed Add-Compare-Select Units using Locally Self-Resetting CMOS", Proc. of 2002 IEEE Int. Symp. on Circuits and Systems, Vol. 1, pp. 889-892, Scottsdale, AZ, May 2002
6. Z. Chi and K.K. Parhi, "High-Speed VLSI Architecture Design for Block Turbo Decoder", Proc. of 2002 IEEE Int. Symp. on Circuits and Systems, Vol. 1, pp. 901-904, Scottsdale, AZ, May 2002
7. Y. Chen and K.K. Parhi, "Parallel Decoding of Interleaved Single Parity Check Turbo Product Codes", Proc. of 2002 IEEE Signal Processing Systems Workshop, pp. 27-32, San Diego, Oct. 2002
8. K.J. Cho, K.C. Lee, J.G. Chung, K.K. Parhi, "Low Error Fixed-Width Modified Booth Multiplier", Proc. of 2002 IEEE Signal Processing Systems Workshop, pp. 45-50, San Diego, Oct. 2002
9. T. Zhang and K.K. Parhi, "A 54 Mbps (3,6)-Regular FPGA LDPC Decoder", Proc. of 2002 IEEE Signal Processing Systems Workshop, pp. 127-132, San Diego, Oct. 2002
10. Y. Chen and K.K. Parhi, "On the Performance and Implementation Implementation of Block Turbo Codes with Antenna Diversity", Proc. of 2002 Asilomar Conf. on Signals, Systems and Computers, Vol. 1, pp. 604-608, Nov. 2002
11. J. Kong and K.K. Parhi, "Viterbi Decoder Architecture for Interleaved Convolutional Code", Proc. of 2002 Asilomar Conf. on Signals, Systems and Computers, Vol. 2, pp. 1934-1937, Nov. 2002

2003

1. J.S. Park, J.-G. Chung, and K.K. Parhi, "An Asynchronous Sample-Rate Converter From CD To DAT", Proc. of IEEE Int. Conf. on Acoustics, Speech and Signal Processing, Vol. 2, pp. 509-512, Hong Kong, April 2003
2. Z. Wang and K.K. Parhi, "Efficient Interleaver Memory Architectures For Serial Turbo Decoding", Proc. of IEEE Int. Conf. on Acoustics, Speech and Signal Processing, Vol. 2, pp. 629-632, Hong Kong, April 2003
3. Y. Chen and K.K. Parhi, "High Throughput Overlapped Message Passing for Low Density Parity Check Codes", Proc. of ACM/IEEE Great Lakes Symp. on VLSI, pp. 245-248, April 2003
4. J.-S. Park, J.-G. Chung and K.K. Parhi, "High-Speed Tunable Fractional-Delay Allpass Filter Structure", Proc. 2003 IEEE Int. Symp. on Circuits and Systems, pp. IV-165-IV-168, Bangkok, May 2003
5. J. Kong and K.K. Parhi, "Low-Latency K-Nested Layered Look-Ahead Method and Architectures for High Throughput Rate Viterbi Decoder", Proc. of 2003 IEEE Workshop on Signal Processing Systems, pp. 99-104, Seoul, Korea, August 2003
6. J. Kong and K.K. Parhi, "Interleaved Cyclic Redundancy Check (CRC) Code", Proc. of 2003 Asilomar Conf. on Signals, Systems and Computers, Vol. 2, pp. 2137-2141, Pacific Grove, CA, Nov. 2003
7. J. Tang and K.K. Parhi, "On the Power Spectrum density and Parameter Choice of Multicarrier UWB Communications" Proc. of 2003 Asilomar Conf. on Signals, Systems and Computers, Vol. 2, pp. 1230-1234, Pacific Grove, CA, Nov. 2003

2004

1. X. Zhang and K.K. Parhi, "High-Speed Architectures for Long BCH Encoders", Proc. of 2004 ACM Great Lakes Symp. on VLSI, pp. 1-6, Boston, April 2004
2. K.K. Parhi, "Novel Pipelining of MSB-First Add-Compare-Select Unit Structure for Viterbi Decoders", Proc. of 2004 IEEE Int. Symp. on Circuits and Systems, Vol. II, pp. 501-504, Vancouver, May 2004
3. Y. Zhang and K.K. Parhi, "Parallel Turbo Decoding", Proc. of 2004 IEEE Int. Symp. on Circuits and Systems, Vol. II, pp. 510-512, Vancouver, May 2004
4. C. Cheng and K.K. Parhi, "Hardware Efficient Fast Parallel FIR Filter Structures Based On Iterated Short Convolution", Proc. of 2004 IEEE Int. Symp. on Circuits and Systems, Vol. III, pp. 361-364, Vancouver, May 2004
5. A. Saberinia, J. Tang, A.H. Tewfik, and K.K. Parhi, "Pulsed OFDM modulation for Ultra wideband Communications", Proc. of 2004 IEEE Int. Symp. on Circuits and Systems, Vol. V, pp. 369-372, Vancouver, May 2004
6. J. Tang, A.H. Tewfik and K.K. Parhi, "High Performance Solution for Interfering UWB Piconets with Reduced Complexity Sphere Decoding", Proc. of 2004 IEEE Int. Symp. on Circuits and Systems, Vol. V, pp. 377-380, Vancouver, May 2004
7. K.K. Parhi, "Pipelining of Parallel Multiplexer Loops and Decision Feedback Equalizers", Proc. of the 2004 IEEE Int. Conf. on Acoustics, Speech and Signal Processing, Vol. V, pp. 21-24, Montreal, May 2004
8. Y. Gu and K.K. Parhi, "Interleaved Trellis Coded Modulation and Decoding for 10 Gigabit Ethernet Over Copper," Proc. of the 2004 IEEE Int. Conf. on Acoustics, Speech and Signal Processing, Vol. V, pp. 25-28, Montreal, May 2004
9. Z. Wang, Y. Chen, and K.K. Parhi, "Area-Efficient Decoding of Quasi-Cyclic Low-Density Parity Check Codes," Proc. of the 2004 IEEE Int. Conf. on Acoustics, Speech and Signal Processing, Vol. V, pp. 49-52, Montreal, May 2004
10. Y. Chen and K.K. Parhi, "Area-Efficient Parallel Decoder Architecture for Long BCH Codes", Proc. of the 2004 IEEE Int. Conf. on Acoustics, Speech and Signal Processing, Vol. V, pp. 73-76, Montreal, May 2004
11. A. Saberinia, J. Tang, A.H. Tewfik, and K.K. Parhi, "Design and Implementation of Multiband Pulsed-OFDM System for Wireless Personal Area Networks, Proc. of 2004 IEEE Int. Conf. on communications, Vol. 2, pp. 862-866, Paris, June 2004
12. K.K. Parhi, "Eliminating the Fanout Bottleneck in Parallel Long BCH Encoders", Proc. of 2004 IEEE Int. Conf. on communications, Vol. 5, pp. 2611-2615, Paris, June 2004
13. J. Tang, A.H. Tewfik and K.K. Parhi, "Reduced Complexity Sphere Decoding and Application to Interfering IEEE 802.15.3a Piconets" Proc. of 2004 IEEE Int. Conf. on communications, Vol. 5, pp. 2864-2868, Paris, June 2004
14. Y. Gu and K.K. Parhi, "Parallel Design for Parallel Decision Feedback Decoders for 10GBASE-T", Proc. of 2004 IEEE Midwest Symp. on Circuits and Systems, pp. II-229-II-232, Hiroshima, Japan, July 2004
15. X. Zhang and K.K. Parhi, "Fast Factorization Architecture in Soft-Decision Reed-Solomon Decoding", Proc. of 2004 IEEE Workshop on Signal Processing Systems, pp. 101-106, Sept. 2004, Austin (TX)
16. S.-M. Kim and K.K. Parhi, "Overlapped Decoding for a Class of Quasi-Cyclic LDPC Codes", Proc. of 2004 IEEE Workshop on Signal Processing Systems, pp. 113-117, Sept. 2004, Austin (TX)
17. Y. Gu and K.K. Parhi, "Complexity Reduction of the Decoders for Interleaved Trellis Coded Modulation Schemes for 10 Gigabit Ethernet over Copper", Proc. of 2004 IEEE Workshop on Signal Processing Systems, pp. 130-135, Sept. 2004, Austin (TX)
18. X. Zhang and K.K. Parhi, "An Efficient 21.5 Gbps AES Implementation on FPGA", Proc. of 38th Asilomar Conference on Signals, Systems, and Computers, Vol. 1, pp. 465-470, Nov. 2004, Pacific Grove (CA)
19. A. E. Cohen and K.K. Parhi, "Implementation of Elliptic Curve Cryptosystem Crypto-Accelerators for GF(2\^m)", Proc. of 38th Asilomar Conference on Signals, Systems, and Computers, Vol. 1, pp. 471-477, Nov. 2004, Pacific Grove (CA)
20. Y. Zhang, Z. Wang and K.K. Parhi, "Efficient High-Speed Quasi-Cyclic LDPC Decoder Architecture", Proc. of 38th Asilomar Conference on Signals, Systems, and Computers, Vol. 1, pp. 540-544, Nov. 2004, Pacific Grove (CA)
21. J. Kong and K.K. Parhi, "Quantum Convolutional Codes Design and their Encoder Architecture", Proc. of 38th Asilomar Conference on Signals, Systems, and Computers, Vol. 1, pp. 1131-1135, Nov. 2004, Pacific Grove (CA)

2005

1. J. Tang and K.K. Parhi, "Viterbi Decoder for High-Speed Ultra-Wideband Communication Systems", Proc. 2005 IEEE Int. Conf. on Acoustics, Speech and Signal Processing, Vol. 5, pp. 37-40, Philadelphia, March 2005
2. A.E. Cohen and K.K. Parhi, "A New Reconfigurable Bit-Serial Systolic Divider for GF(2\^m) and GF(p)", Proc. 2005 IEEE Int. Conf. on Acoustics, Speech and Signal Processing, Vol. 5, pp. 105-108, Philadelphia, March 2005
3. Y. Gu and K.K. Parhi, "Pipelined Parallel Decision Feedback Decoders (PDFDs) for High-Speed Ethernet over Copper", Proc. 2005 IEEE Int. Conf. on Acoustics, Speech and Signal Processing, Vol. 5, 121-124, Philadelphia, March 2005
4. S.-M. Kim, J. Tang and K.K. Parhi, "Quasi-Cyclic Low-Density Parity-Check Coded Multiband-OFDM UWB Systems", Proc. of 2005 IEEE Int. Symposium on Circuits and Systems, pp. 65-68, Kobe (Japan), May 2005
5. Y. Gu and K.K. Parhi, "Pipelining Tomlinson-Harashima Precoders", Proc. of 2005 IEEE Int. Symposium on Circuits and Systems, pp. 408-411, Kobe (Japan), May 2005
6. C. Cheng and K.K. Parhi, "Further Complexity Reduction of Parallel FIR Filters", Proc. of 2005 IEEE Int. Symposium on Circuits and Systems, pp. 1835-1838, Kobe (Japan), May 2005
7. J. Lin and K.K. Parhi, "VLSI Architectures for Stereoscopic Video, Disparity Matching and Object Extraction", Proc. of 2005 IEEE Int. Symposium on Circuits and Systems, pp. 2373-2376, Kobe (Japan), May 2005
8. C. Cheng and K.K. Parhi, "Low-Cost Parallel Adaptive Filter Structures", Proc. of 39th Asilomar Conference on Signals, Systems, and Computers, pp. 354-358, Nov. 2005, Pacific Grove (CA)
9. M. Yadav and K.K. Parhi, "Design and Implementation of LDPC Codes for DVB-S2", Proc. of 39th Asilomar Conference on Signals, Systems, and Computers, pp. 723-728, Oct. 2005, Pacific Grove (CA)

2006

1. J. Chen, Y. Gu and K.K. Parhi, "MIMO Equalization and Cancellation for 10Gbase-T", Proc. of 2006 IEEE Int. Conf. Acoustics, Speech and Signal Processing, pp. IV-637-IV-640, Toulouse (France), May 2006
2. J. Lee, S. Park, Y. Zhang, K.K. Parhi, and S.-C. Park, "Implementation Issues of a List Sphere Decoder", Proc. of 2006 IEEE Int. Conf. Acoustics, Speech and Signal Processing, pp. III-996-III-999, Toulouse (France), May 2006
3. S. Park, K. Lee, Y. Zhang, K.K. Parhi, J. Lee, S.-C. Park, "Probabilistic List Sphere Decoding for LDPC-Coded MIMO-OFDM Systems", Proc. of 2006 IEEE Int. Conf. Acoustics, Speech and Signal Processing, pp. III-912-III-915, Toulouse (France), May 2006
4. Z. Wang, Y. Zhang and K.K. Parhi, "Study of Early Stopping Criteria for Turbo Decoding and Their Applications in WCDMA Systems", Proc. of 2006 IEEE Int. Conf. Acoustics, Speech and Signal Processing, pp. III-1016-III-1019, Toulouse (France), May 2006
5. A.E. Cohen and K.K. Parhi, "Faster elliptic curve point multiplication based on a novel greedy base-2,3 method", Proc. of 2006 IEEE Int. Symp. on Circuits and Systems, pp. 3374-3377, Kos (Greece), May 2006
6. J. Lin and K.K. Parhi, "Low-Complexity Block Turbo Equalization", Proc. of 2006 IEEE Int. Symp. on Circuits and Systems, pp. 5091-5094, Kos (Greece), May 2006
7. J. Tang, T. Bhatt, V. Sundaramurthy, "Reconfigurable Shuffle Network Design in LDPC Decoders", Proc. of 2006 IEEE Conf. on Applications-Specific Architectures, Systems, and Processors, pp. 81-86, Steamboat Springs (CO), Sept. 2006
8. D. Oh and K.K. Parhi, "Low Complexity Design of High-Speed Parallel Decision Feedback Equalizers", Proc. of 2006 IEEE Conf. on Applications-Specific Architectures, Systems, and Processors, pp. 118-122, Steamboat Springs (CO), Sept. 2006
9. Y. Zhang, J. Tang and K.K. Parhi, "Low-Complexity List Updating Circuits for List Sphere Decoders", Proc. 2006 IEEE Workshop on Signal Processing Systems, pp. 28-33, Banff, Canada, Oct. 2006
10. J. Lin and K.K. Parhi, "Low Complexity Iterative Joint Detection, Decoding, and Channel Estimation for Wireless MIMO System", Proc. 2006 IEEE Workshop on Signal Processing Systems, pp. 45-50, Banff, Canada, Oct. 2006
11. J. Chen and K.K. Parhi, "Adaptive Tap Management in Multi-Gigabit Echo and NEXT Cancellers", Proc. 2006 IEEE Workshop on Signal Processing Systems, pp. 415-419, Banff, Canada, Oct. 2006
12. D. Oh and K.K. Parhi, "Low-Complexity Implementations of Sum-Product Algorithm for Decoding Low-Density Parity Check Codes", Proc. 2006 IEEE Workshop on Signal Processing Systems, pp. 262-267, Banff, Canada, Oct. 2006
13. J. Lin and K.K. Parhi, "High-Speed Error Resilient Stereoscopic Video Coder", Proc. of 40th Asilomar Conf. on Signals, Systems and Computers, Oct. 2006, pp. 1054-1058, Pacific Grove (CA)
14. A.E. Cohen and K.K. Parhi, "New Side Channel Resistant Scalar Point Multiplication Method for Binary Elliptic Curves", Proc. of 40th Asilomar Conf. on Signals, Systems and Computers, Oct. 2006, pp. 1205-1209, Pacific Grove (CA)
15. Y. Zhang and K.K. Parhi, "High-Throughput Radix-4 LogMAP Turbo Decoder Architecture", Proc. of 40th Asilomar Conf. on Signals, Systems and Computers, Oct. 2006, pp. 1711-1715, Pacific Grove (CA)
16. Y. Zhang, J. Tang and K.K. Parhi, "Low Complexity Radius Reduction Method for List Sphere Decoders", Proc. of 40th Asilomar Conf. on Signals, Systems and Computers, Oct. 2006, pp. 2200-2203, Pacific Grove (CA)