Ph.D. Theses Supervised:

  1. Ching-Yi Wang, "MARS: A High-Level Synthesis Tool for Digital Signal Processing Architecture Design", December 1992, (Currently with Guidant Corp., St. Paul)
  2. Lori E. Lucke, "Applying Parallel Processing Techniques to Digital Signal Processing Algorithms and Architectures for High-Level VLSI Synthesis", December 1992 (Currently with Minnetronix, St. Paul)
  3. Naresh R. Shanbhag, "Design of Pipelined VLSI Adaptive Digital Filters with Relaxed Look-Ahead", July 1993 (Currently Professor of ECE at Univ. of Illinois , Urbana)
  4. H.R. Srinivas, "Floating Point Computer Arithmetic Architectures", September 1994, (Currently with Broadcom, Irvine, CA)
  5. K.J. Raghunath, "Pipelined STAR RLS Adaptive Filters", October 1994, (Currently with Sandbridge, NY)
  6. Jin-Gyun Chung, "Pipelined IIR Lattice and Wave Digital Filters", November 1994, (Currently with Chonbuk National University , Chonju, S. Korea)
  7. Tracy C. Denk, "Retiming, Folding and Register Minimization", July 1996, (Currently with Newport Media Inc. , Irvine, CA)
  8. Janardhan H. Satyanarayana, "Design of Low-Power DSP Systems", March 1998, (Currently with Agere Systems, Allentown, PA)
  9. Ahmed Shalash, "Architecture and System Design for Digital Subscriber Loop Communications", June 1998, (Currently with Analog Devices, Somerset, NJ)
  10. Leilei Song, "Low-Power VLSI Architectures for Finite-Field Applications", June 1999, (Currently with Marvell Technology Group, Santa Clara, CA)
  11. Yun-Nan Chang, "Low-Power Bit-Serial and Digit-Serial DSP Systems", June 1999, (Currently with National Sun Yat-Sen University, Kaohsiung, Taiwan)
  12. Jun Ma, "Pipelined RLS Adaptive Filters", July 1999, (Currently with Newport Media Inc., Irvine, CA)
  13. Martin Kuhlmann, "High-Performance Low-Power Arithmetic Architectures and Circuits", Dec. 1999 (Currently with Broadcom, Irvine, CA)
  14. Vijay Sundararajan, "Performance Optimization Methodologies for Design of Digital VLSI Systems", Jan. 2000 (Currently with Texas Instruments, Dallas)
  15. Zhongfeng Wang, "High-Performance and Low-Cost VLSI Design of Turbo Decoders", Aug. 2000, (Currently with Broadcom Corp, Irvine, CA)
  16. Robert A. Freking, "Structural Strategies for High-Performance Undelimited-Codeword Source Coding", Oct. 2000, (Currently with M.I.T. Lincoln Laboratories, MA)
  17. William L. Freking, "Algorithms and Architectures for High-Performance Public-Key Cryptosystems", October 2000 (Currently with M.I.T. Lincoln Laboratories, MA)
  18. Lijun Gao, "Architecture Design and Mapping of DSP Systems", Feb. 2001, (Currently with Medtronic, Minneapolis)
  19. Zhipei Chi, "High-Performance, High-Speed VLSI Architectures for Wireless Communications Applications", June 2001, (Currently with Marvell Technology Group, Calif.)
  20. Tong Zhang, "Efficient VLSI Architectures for Error-Correction Coding", June 2002, (Currently Assistant Professor, Dept. ECSE, RPI, Troy, NY)
  21. Yanni Chen, "Low-Complexity High-Speed VLSI Architectures for Error-Correction Decoders", May 2003, (Currently with Marvell Technology Group, Santa Clara, CA)
  22. Jun Jin Kong, "Classical and Quantum Convolutional Codes: Design and Implementation", Feb. 2005, (Currently with Samsung, Korea)
  23. Xinmiao Zhang, "Architectures for Error Control Coders and Cryptography Systems", June 2005, (Currently Assistant Professor at Case Western Reserve University, Cleveland, Ohio)
  24. Yongru Gu, "VLSI Architectures for High-Speed Transceivers", July 2005, (Currently with Newport Media Inc., Irvine, CA)
  25. Jun Tang, "Architectures for OFDM Based Ultra Wideband Systems", August 2006, (Currently with Newport Media Inc., Irvine, CA)
  26. Sang-Min Kim, "Efficient VLSI Architectures for Error Control Coders", October 2006, (Currently with Qualcomm, San Diego, CA)
  27. Jianhung Lin, "Algorithms and Architectures for Next Generation Multimedia Communications Systems", January 2007, (Currently with Newport Media Inc., Irvine, CA)
  28. Yuping Zhang, "VLSI Architectures for Turbo Code Decoder, LDPC Code Decoder and List Sphere Decoder", May 2007, (Currently with Marvell Technology Group, Santa Clara, CA)
  29. Chao Cheng, "High-Speed Low-Cost VLSI DSP Algorithms Based on Novel Fast Convolutions and Look-Ahead Pipelining Structures" May 2007, (Currently with Marvell Technology Group, Santa Clara, CA)
  30. Aaron E. Cohen, "Architectures for Cryptography Accelerators", September 2007,

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