Crypto Accelerators

Overview

Cryptography has become a necessity in today's world where data is easily intercepted and copied. Accelerating cryptography has become important for low power devices, routers, and servers. Low power devices would suffer considerable latency without the aid of crypto accelerators. Similarly, routers and servers would not be able to meet the throughput requirements for secure connections without crypto accelerators. Our research has focused on both public key crypto acceleration and symmetric key crypto acceleration. We have developed high throughput crypto accelerator architectures for the Advanced Encryption Standard (AES), the RSA Cryptosystem, and Elliptic Curve Cryptosystems. In 2004, we developed a high speed (21.56 Gbps) FPGA implementation of the AES utilizing a combination of subpipelining and composite field S-Box implementation instead of lookup tables. As for public key cryptography, we have successfully designed an RNS Montgomery multiplier method which does not require CRT base extension but instead utilizes the Montgomery multiplication principle. By folding the systolic array for the Montgomery multiplier twice and using retiming we have designed ring planarized cylindrical arrays which achieve nearest neighbor communication with a linear (not quadratic) increase in total delay elements. Our more recent efforts in elliptic curve cryptography include investigating reconfigurable architectures for GF(p) and GF(2m) and designing cryptographic scalable crypto accelerators.

Related Papers

  • A. E. Cohen and K. K. Parhi, "Implementation of scalable elliptic curve cryptosystem crypto-accelerators for GF(2m)," Thirty-Eighth Asilomar Conference on Signals, Systems and Computers, vol. 1, pp. 471 - 477, Nov. 7-10, 2004
  • A. E. Cohen and K. K. Parhi, "A New Reconfigurable Bit-Serial Systolic Divider for GF(2m) and GF(p)," IEEE International Conference on Acoustics, Speech, and Signal Processing, (ICASSP '05), vol. 5, pp. 105 - 108, March 18-23, 2005
  • W. L. Freking and K. K. Parhi, "Modular multiplication in the residue number system with application to massively-parallel public-key cryptography systems," Thirty-Fourth Asilomar Conference on Signals, Systems and Computers, vol. 2, pp. 1339 - 1343, Oct. 29 - Nov. 1, 2000
  • W. L. Freking and K. K. Parhi, "Ring-planarized cylindrical arrays with application to modular multiplication," IEEE Workshop on Signal Processing Systems, SiPS 2000, Page(s):497 - 506, Oct. 11-13, 2000
  • W. L. Freking and K. K. Parhi, "Performance-scalable array architectures for modular multiplication," IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2000, pp. 149 - 160, July 10-12, 2000
  • W. L. Freking and K. K. Parhi, "A unified method for iterative computation of modular multiplication and reduction operations," International Conference on Computer Design, 1999. (ICCD '99), pp. 80 - 87, Oct. 10-13, 1999
  • W. L. Freking and K. K. Parhi, "Montgomery modular multiplication and exponentiation in the residue number system," Thirty-Third Asilomar Conference on Signals, Systems, and Computers, vol. 2, pp. 1312 - 1316, Oct. 24-27, 1999
  • W. L. Freking and K. K. Parhi, "Parallel modular multiplication with application to VLSI RSA implementation," IEEE International Symposium on Circuits and Systems, ISCAS '99, vol. 1, pp. 490 - 495, May 30 -June 2, 1999
  • X. Zhang and K. K. Parhi, "An efficient 21.56 Gbps AES implementation on FPGA," Thirty-Eighth Asilomar Conference on Signals, Systems and Computers, vol. 1, pp. 465 - 470, Nov. 7-10, 2004
  • X. Zhang and K. K. Parhi, "Implementation approaches for the Advanced Encryption Standard algorithm," IEEE Circuits and Systems Magazine, vol. 2, no. 4, pp. 24 - 46
  • X. Zhang and K. K. Parhi, "High-speed VLSI architectures for the AES algorithm," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 9, pp. 957 - 967, Sept. 2004
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