VLSI Digital Filters and LFSR Circuits

Overview
Our current research interests in this area include: 1) Applications of fast algorithms: Parallel FIR filter structures; High speed DCT, DFT and DWT; Parallel FIR adaptive filter structures; 2) High speed circuit design based on VLSI DSP algorithms: Parallel CRC; General Parallel Linear Feedback Shift Register Implementation.

Related Papers

K. K. Parhi, "Eliminating the Fanout Bottleneck in Parallel Long BCH Encoders", IEEE Trans. on Circuits and Systems, Part-I: Regular Papers, 51(3), pp. 512-516, March 2004

X. Zhang and K. K. Parhi, “High-speed Architectures for Parallel Long BCH encoders,” Proc. of ACM Great Lake Symposium on VLSI, pp. 1-6, Boston, Massachusetts, Apr. 2004. (Best Paper Award)

Xinmiao Zhang and Keshab K. Parhi, "High-speed Architectures for Parallel Long BCH Encoders," IEEE Trans. on VLSI Systems, Vol. 13, No. 7, pp. 872-877, July 2005

C. Cheng and K.K. Parhi, "Hardware Efficient Fast Parallel FIR Filter Structures Based on Iterated Short Convolution", IEEE Trans. on Circuits and Systems, Part-I: Regular Papers, 51(8), pp. 1492-1500, Aug. 2004

C. Cheng and K.K. Parhi, "A Novel Systolic Array Structure for DCT", IEEE Trans. on Circuits and Systems, Part-II: Express Briefs, 52(5), pp. 366-3689, July 2005

C. Cheng and K.K. Parhi, "Further Complexity Reduction of Parallel FIR Filters", Proc. of 2005 IEEE Int. Symposium on Circuits and Systems, pp. 1835-1838, Kobe (Japan), May 2005

C. Cheng and K.K. Parhi, "Low-Cost Parallel Adaptive Filter Structures", Proc. of 39th Asilomar Conference on Signals, Systems, and Computers, Nov. 2005, Pacific Grove, CA

C. Cheng and K. K. Parhi, "Hardware Efficient Fast Computation of the Discrete Fourier Transform," Journal of VLSI signal processing, Accepted on June 20, 2005.

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