Computing with Reliable Algorithms and Unreliable Memories

Prof. Rakesh Kumar
University of Illinois - Urbana-Champaign

Abstract:
Although computational systems are looking towards post CMOS devices in the pursuit of scalability and lower power, the inherent unreliability of such devices makes it difficult to design robust systems at acceptable efficiencies.  In this talk, I will discuss two research efforts within my group that address computing with fault prone devices. The first effort attempts to utilize algorithmic structures with inherent ability to tolerate computational errors as templates for building computer systems. Specifically, we propose to cast applications as  sampling-based algorithms based on Markov chains as such algorithms are both sufficiently general and tolerant to transition errors. We also look at other sampling-based implementations. Our second research effort focuses on computing in presence of high fault rates in memories. I will discuss techniques such as speculative error correction that allow memories to operate robustly without the latency overheads of strong ECC schemes.

Bio:
Rakesh Kumar is an Associate Professor in the Electrical and Computer Engineering Department at the University of Illinois at Urbana Champaign and a Co-Founder and Chief Architect at Hyperion Core, Inc. His current research interests are in computer architecture, stochastic and approximate computing, low power and error resilient computer systems, and architectures for inference and machine learning. His research recognitions include several best paper awards and best paper award nominations, ARO Young Investigator Award, Arnold O Beckman Research Award, FAA Creative Research Award, UCSD CSE Best Dissertation Award, and an IBM PhD Fellowship. Teaching recognitions include appearance on UIUC's List of Teachers Ranked as Excellent. Advising recognitions include Engineering Council Outstanding Advisor Award. Rakesh has a BS from IIT Kharagpur and a PhD from University of California at San Diego.