Scaling the Memory Wall for Exascale HPC Systems

Daniel Ernst, PhD
Cray Hardware System Architecture

Abstract:
The chase for peak floating point performance in HPC systems has been proceeding at a “Moore’s Law” pace for over three decades, showing up in flashy bi-annual lists and resulting news articles.  However, this chase for “peak” has focused budgeted resources on microprocessors, with very little attention paid to the supporting system components, such as the memory system, required to keep floating point units well-supplied with data.  As a result, sustained application performance has been increasing at a much slower pace, slowing almost to a complete stop in the current “Petascale Era”.
 
In order to provide productive sustained performance at the Exascale, HPC researchers and developers are refocusing their efforts on breaking through the data movement bottleneck in the memory system.  This presentation will give an HPC perspective on some of the technologies being developed and deployed in the industry as part of this effort, including 3D stacked memory, high-bandwidth and abstract interfaces, and non-volatile memories.
 
Bio:
Daniel Ernst is a member of Cray’s Hardware System Architecture team where his current focus is on high-performance memory systems, application-optimized architectures, future node architectures, and system simulation.  Daniel was previously an architect for Cray’s Custom Engineering team where he performed studies directly with customers exploring custom system solutions for a focused group of applications.  He has published papers on microprocessor architectures for performance, power-efficiency, and reliability, as well as the development of flexible simulation tools.  Daniel is currently Cray’s representative to the JEDEC memory standards committees.  Daniel received his Ph.D. in Computer Science and Engineering from the University of Michigan in 2005, where he studied high-performance, low-power, and fault-tolerant microarchitectures.  He also holds an MSE from Michigan and a BS in Computer Engineering from Iowa State University.