Tunneling Field-Effect Transistors: Are They a Solution to the Power Problem in Computational Systems?

Steven J. Koester
Department of Electrical & Computer Engineering, University of Minnesota

Abstract
Power dissipation in CMOS logic circuits is the primary barrier limiting scaling to future technology nodes. The most effective way to reduce power consumption is to drop the supply voltage, but in conventional CMOS this leads to an unacceptable tradeoff between maintaining performance and increasing leakage power. The origin of this problem can be traced back to the thermionic turn-off mechanism of MOSFETs which requires at least 60 mV of gate voltage swing to reduce the drain current by one order of magnitude. Tunneling field-effect transistors (TFETs) are a new class of devices that theoretically can provide less than 60 mV/decade drain current modulation owing to their non-thermionic turn-off mechanism. However, TFET research is in its infancy, and devices demonstrated to date have drive current that is too low for practical applications.  In this presentation, I provide an overview of the field of TFET research. I explain the physics of the device operation, survey the previous literature, and describe efforts to improve the device performance using heterostructure engineering. This description includes recent experimental results from IBM on Si/SiGe heterojunction TFETs that show improved performance compared to Si homojunction devices. I will then discuss a new TFET device concept that promises to enhance the performance further, and also describe trap-assisted and phonon-assisted tunneling mechanisms that could negate these performance improvements.

Biography
Dr. Koester is a Professor of Electrical and Computer Engineering at the University of Minnesota.  Prior to joining Minnesota, he was a Research Staff Member at the IBM T. J. Watson Research Center.  His most recent position at IBM was Manager of Exploratory Technology where his team investigated novel device and integration solutions for post 22-nm-node CMOS technology. Dr. Koester received his Ph.D. in 1995 from the University of California, Santa Barbara, where his research involved the study of quantum transport in InAs quasi-one-dimensional structures. He also received M.S.E.E and B.S.E.E. degrees from the University of Notre Dame in 1991 and 1989, respectively. Dr. Koester has authored or co-authored over 125 technical publications and conference presentations, and holds 22 United States patents.