Forward Error Correction Architectures for 100 Gb/s Optical Communications

Prof. Hanho Lee
Inha University, South Korea

Abstract:
The role of forward error correction (FEC) has become of critical importance in fiber optic communications, as backbone networks increase in speed to 40 and 100 Gb/s, particularly as poor optical-signal-to-noise environments are encountered. Also, the development of very high-speed data transmission techniques for optical fiber communication systems have necessitated the implementation of high speed enhanced FEC architectures to meet the continuing demand for ever-higher data rates. In this talk, a broad overview of next-generation enhanced FEC codes and architectures, such as block codes and concatenated codes, for optical communications will be addressed. A novel enhanced FEC scheme which is the concatenation of an LDPC code and a hard-decision FEC code will be presented.

Affiliation:
Hanho Lee, Ph.D
Associate Professor
Dept. of Information and Communication Engr.
Inha University, South Korea
Email: hhlee@inha.ac.kr

Biography:
Hanho Lee received Ph.D. and M.S. degrees, both in Electrical & Computer Engineering, from the University of Minnesota, Minneapolis, in 2000 and 1996 respectively, and a B.S. degree in Electronics Engineering from Chungbuk National University, South Korea, in 1993. In 1999, he was a Member of Technical-Staff-1 at Lucent Technologies, Bell Labs, Holmdel, NJ. From April 2000 to August 2002, he was a Member of Technical Staff at the Lucent Technologies (Bell Labs Innovations), Allentown, where he was responsible for the development of VLSI architecture of digital signal processing multiprocessor for wireless infrastructure systems. From August 2002 to August 2004, he was an assistant professor at the Department of Electrical and Computer Engineering, University of Connecticut, Storrs. Since August 2004, he has been with the School of Information and Communication Engineering, Inha University, where he is presently an associate professor. He was a visiting researcher at the Electronics and Telecommunications Research Institute (ETRI) in 2005. Currently, he is a visiting scholar at Bell Labs, Alcatel-Lucent, Murray Hill, New Jersey. His research interests include VLSI architecture design for digital signal processing and communications, and forward error correction architectures.