Turning Dark Silicon into Green through Ultra Energy?Efficient VLSI Circuits from Nano to Macro Scale

Massimo Alioto, Ph.D.
Visiting Professor at EECS – University of Michigan, Ann Arbor
Associate Professor of Electronics ? University of Sienna


ABSTRACT
In the last few years, evolution of CMOS VLSI circuits has significantly departed from the historical Dennard’s scaling trends, mostly for reasons related to energy efficiency. The current multi?core era promises sustainable technology scaling thanks to a more efficient utilization of energy. Unfortunately, very recent projections show that multi?core scaling is likely to come to an end in a relatively short amount of time (∼5 years), since inadequate energy efficiency makes it impossible to fully utilize all the devices available in a chip. The increasing fraction of circuits that cannot be used at the same time in the same chip (“dark silicon”) will eventually nullify the benefits brought by the exponential increase in transistors per chip as per Moore’s law. Hence, dark silicon is a very serious threat to the continuation of CMOS scaling and hence to the business model adopted by the semiconductor industry. In this talk, the “dark silicon” issue is put into the broader perspective of computing and sensing platforms that expand towards the nano (ubiquitous computing/sensing) and the macro scale (cloud computing). Dramatic improvements in the energy efficiency (“green silicon”) of such platforms are clearly required to avoid or limit dark silicon and maintain the benefits of technology scaling in the next decade. The talk focuses on VLSI circuit design aspects from the nano to the macro scale, and presents new ideas to “turn dark silicon into green silicon”, thus postponing the end of the CMOS scaling era.

At the nano scale, ideas and methodologies are discussed for ultra?compact active RFIDs with perpetual operation as general?purpose sensing platform (e.g., for smart buildings, pervasive security). As a focus on the topic, recent circuit techniques in DC?DC converters for μW or sub?μW applications are introduced, and results in 65?nm test chips are discussed. At the macro scale, innovative methodologies and circuit topologies to reduce the consumption of energy?hungry clock domains in high?performance microprocessors (e.g., for servers) will be introduced.

Experimental results in 65?nm test chips are discussed to demonstrate 2X improvement in energy efficiency compared to the state of the art. At the intermediate “meso scale” of portable and mobile electronics, the wide concept of “energy scalability” is explored in the context of nearthreshold SRAM memories to achieve another 2X better energy efficiency. Energy reduction is here pursued by broadly looking at the resulting quality of the processed signal and the user experience (e.g., video streaming devices), rather than narrow design considerations at circuit level.

Finally, new directions and promising ideas on how to “turn dark into green silicon” will be openly discussed to provide a long?term perspective on this grand challenge and related solutions. A view on how to take full advantage of the proposed circuit advances at the system level will be also presented to better understand the tight relation with the evolution of neighboring research fields.

SHORT BIO:
Massimo Alioto (M’01–SM’07) was born in Brescia, Italy, in 1972. He received the laurea degree in Electronics Engineering and the Ph.D. degree in Electrical Engineering from the University of Catania (Italy) in 1997 and 2001, respectively. In 2002, he joined the Dipartimento di Ingegneria dell’Informazione (DII) of the University of Siena as a Research Associate and in the same year as an Assistant Professor. In 2005 he was appointed Associate Professor of Electronics, and was engaged in the same faculty in 2006. In the summer of 2007, he was a Visiting Professor at EPFL ? Lausanne (Switzerland). In 2009?2011, he is Visiting Professor at BWRC – UCBerkeley, investigating on next?generation ultra?low power circuits and wireless sensor nodes, and in 2011?2012 also at EECS – Umichigan to work on ultra?energy efficient resilient computing. Since 2001 he has been teaching undergraduate and graduate courses on advanced VLSI digital design, microelectronics and basic electronics.

He has authored or co?authored about 170 publications on journals (60, mostly IEEE Transactions) and conference proceedings. Two of them are among the most downloaded TVLSI papers in 2007 (respectively 10th and 13th). He is coauthor of the book Model and Design of Bipolar and MOS Current?Mode Logic: CML, ECL and SCL Digital Circuits (Springer, 2005).

His primary research interests include ultra low?power circuits for ubiquitous computing and self?powered sensor nodes, active techniques for resilient energy efficient computing and timing speculation, leakage? and variability?aware design methodologies, circuit techniques in emerging technologies (FinFET, Tunnel FET, Ge and Si?Ge MOS), Current?Mode Logic circuits, cryptographic circuits resistant to side?channel attacks and ultra?low power/area/design cost schemes for information security, low?standby current caches. He is the director of the Electronics Lab at University of Siena (site of Arezzo).

Prof. Alioto is an IEEE Senior Member and a member of the HiPEAC Network of Excellence. He is the Chair of the “VLSI Systems and Applications” Technical Committee of the IEEE Circuits and Systems Society, for which he is also Distinguished Lecturer. He is regularly invited to give talks and tutorials to academic institutions, conferences and companies throughout the world. He serves or has served as a member of various conference technical program committees (ISCAS, ICCD, PATMOS, ICM, ECCTD, CSIE) and Track Chair (ISCAS, ICCD, ICECS, ICM). He currently serves as Associate Editor of the IEEE Transactions on VLSI Systems, as well as of the ACM Transactions on Design Automation of Electronic Systems, IEEE Transactions on Circuits – part I, Microelectronics Journal, Integration – The VLSI journal, the Journal of Circuits, Systems, and Computers, the Journal of Low Power Electronics, the Journal of Low Power Electronics and Applications. He was Guest Editor of the Special Issue “Advances in oscillator analysis and design” of the Journal of Circuits, Systems, and Computers (2010), and Technical Program Chair for the ICM 2010 and NEWCAS 2012 conferences.