Compact Models for Beyond CMOS Spintronic Devices and Interconnects

Azad Naeemi
Georgia Institute of Technology

Abstract:
As Si CMOS technology approaches its scaling limits, there is a global search for novel devices based on state variables other than electronic charge. Among the potential alternative state variables, electron spin has received special attention thanks to its advantages in terms of robustness, non-volatility, and enhanced functionality. This talk will focus on compact physical models for novel spintronic devices and interconnects for all-spin-logic and spinwave circuits. At the material level, compact models will be presented for spin transport parameters in Cu, Al, Si, and GaAs. At the device level, spin injection efficiency has been modeled by solving Poisson and Schrödinger equations self consistently. At the circuit level, a comprehensive set of SPICE models are developed for nanomagnet dynamics, spin injection and extraction, spin drift and diffusion, and spin wave generation and propagation. The models provide a powerful platform to model, optimize and benchmark various spin-based devices, interconnects, and circuits in a unified and efficient fashion.  

Bio
Azad Naeemi is an Associate Professor in the School of ECE at the Georgia Institute of Technology. He worked as a research engineer in the Microelectronics Research Center at Georgia Tech from 2004 to 2008 and joined the ECE faculty at Georgia Tech in fall 2008. His primary area of interest is exploring nanotechnology solutions to the challenges facing giga- and terascale systems. Dr. Naeemi is the recipient of the IEEE Electron Devices Society (EDS) Paul Rappaport Award for the best paper that appeared in the IEEE Transactions on Electron Devices during 2007. He has also received an NSF CAREER Award and an SRC Inventor Recognition Award.