Variation-Tolerant Computer Architectures

Josep Torrellas
Professor, Computer Science Department
University of Illinois, Urbana-Champaign
http://iacoma.cs.uiuc.edu/~torrellas

Abstract - Dealing with parameter variation in a cost-effective manner is one of the main challenges faced by multicore developers. This challenge is best addressed at multiple levels, including the device, circuits, architecture, and software layers. This talk presents some of the new approaches that we have developed at the architecture level. In particular, we show how aging can be traded-off for power and performance, giving rise to a new way to speed-up single thread performance that we call BubbleWrap. We also present our work on near-threshold voltage operation, and show a new way to cope with process variation with simple architectural support.

Bio - Josep Torrellas (http://iacoma.cs.uiuc.edu) is a Professor at the University of Illinois. Prior to being at Illinois, Torrellas received a PhD from Stanford University. He also spent a year IBM's T.J. Watson Research Center. Torrellas' research area is multiprocessor computer architecture. He leads the Bulk Multicore Architecture for programmability. Prior to that, he led the Illinois Aggressive COMA Multiprocessor project and had been involved in the Stanford DASH and the Illinois Cedar multiprocessor projects. He has contributed extensively in the area of shared-memory multiprocessor architecture and thread-level speculation.