- Y. Xie, J. Cong, and S. Sapatnekar, editors,
*Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures*, Springer, Boston, MA, 2010. - C. J. Alpert, D. P. Mehta, and S. S. Sapatnekar, editors,
*Handbook of Algorithms for VLSI Physical Design Automation*, CRC Press, New York, NY, 2008.

- P. Saxena, R. S. Shelar, and S. S. Sapatnekar,
*Routing Congestion in VLSI Circuits*, Springer, Boston, MA, 2007. - D. J. Lilja and S. S. Sapatnekar,
*Designing Digital Computing Systems with Verilog*, Cambridge University Press, Cambridge, UK, 2005. - S. S. Sapatnekar,
*Timing*, Kluwer Academic Publishers, Boston, MA, 2004. - B. Lu, D.-Z. Du, and S. S. Sapatnekar, editors,
*Layout Optimization in VLSI Design*, Kluwer Academic Publishers, Boston, MA, 2001. - N. Maheshwari and S. S. Sapatnekar,
*Timing Analysis and Optimization of Sequential Circuits*, Kluwer Academic Publishers, Boston, MA, 1999. - S. S. Sapatnekar and S. M. Kang,
*Design Automation for Timing-Driven Layout Synthesis*, Kluwer Academic Publishers, Boston, MA, 1993.

- S. S. Sapatnekar, “Statistical Design of Integrated Circuits,” in
Low-Power Variation-Tolerant
Design in Nanometer Silicon, S. Bhunia and S. Mukhopadhyay, eds.
Springer, Boston, MA, 2011.

- S. S. Sapatnekar, “Thermal and Power Delivery Challenges in 3D
ICs,” in
*Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures*, Y. Xie, J. Cong, and S. Sapatnekar, eds.,

Springer, Boston, MA, 2010. - S. S. Sapatnekar, “Thermal Via Insertion and Thermally Aware
Routing in 3D ICs,” in
*Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures*, Y. Xie, J. Cong, and S. Sapatnekar, eds., Springer, Boston, MA, 2010. - S. S. Sapatnekar, “Computer-Aided Design for 3D Circuits,” in
*3D IC Integration: Technology and Applications*, P. Ramm, C. Bower, P. Garrou, eds., Wiley-VCH, Weinheim, Germany, 2008. - K. Bazargan and S. S. Sapatnekar, “Physical Design for 3D
Circuits,” in
*The Handbook of Algorithms for VLSI Physical Design Automation,*C. J. Alpert, D. P. Mehta, and S. S. Sapatnekar, eds., CRC Press, 2008. - F. Liu and S. S. Sapatnekar, “Metrics Used in Physical Design,”
in
*The Handbook of Algorithms for VLSI Physical Design Automation*, C. J. Alpert, D. P. Mehta, and S. S. Sapatnekar, eds., CRC Press, 2008. - S. S. Sapatnekar, “Static Timing Analysis,” in
*The CRC Handbook of EDA for IC Design*, L. Scheffer, L. Lavagno, and G. Martin, eds., pp. 6-1 . 6-17, CRC Press, Boca Raton, FL, 2006. - S. S. Sapatnekar, “Convex Optimization,” in
*The Wiley Encyclopedia of Computer Science and Engineering*, J. G. Webster, ed., John Wiley and Sons, New York, NY (in press). - J. Hu and S. S. Sapatnekar, “Non-Hanan Optimization for Global
VLSI Interconnect,” in
*Layout Optimizations in VLSI Design*, B. Lu, D.-Z. Du, and S. S. Sapatnekar, ed., Kluwer Academic Publishers, Boston, MA, 2001. - S. S. Sapatnekar, “Circuit Optimization,” in
*The Wiley Encyclopedia of Electrical and Electronics Engineering*, J. G. Webster, ed., John Wiley and Sons, New York, NY, 2001. - S. S. Sapatnekar, “Convex Optimization,” in
*The Wiley Encyclopedia of Electrical and Electronics Engineering*, J. G. Webster, ed., Vol. 4, John Wiley, New York, NY, 1999. - S. S. Sapatnekar, “Design by Optimization,” in
*The Circuits and Filters Handbook*, ed. W.-K. Chen, CRC Press, 1995.

- B. Boghrati and S. S. Sapatnekar, “Incremental Analysis of Power Grids using Backward Random Walks,” accepted for publication in the ACM Transactions on Design Automation of Electronic Systems, 2014.

- Y. Wei, C. Sze, N. Viswanathan, Z. Li, C. J. Alpert, L. Reddy, A. D. Huber, G. E. Tellez, D. Keller, and S. S. Sapatnekar, “Techniques for Scalable and Effective Routability Evaluation,” ACM Transactions on Design Automation of Electronic Systems, Vol. 19, No. 2, Article No. 17, March 2014.

- P. Zhou, A. Paul, C. H. Kim, and S. S. Sapatnekar, “Distributed
On-Chip Switched-Capacitor DC-DC Converters Supporting DVFS in
Multicore Systems,” accepted for publication in the IEEE Transactions on VLSI Systems, 2013.

- J. Fang and S. S. Sapatnekar, “Incorporating Hot Carrier Injection Effects into Timing Analysis for Large Circuits,” accepted for publication in the IEEE Transactions on VLSI Systems, 2013.

- S. Gupta and S. S. Sapatnekar, “Variation-Aware Design of Variable Latency Units,” accepted for publication in the IEEE Transactions on VLSI Systems, 2013.
- S. Gupta and S. S. Sapatnekar, “Employing Circadian Rhythms to Enhance Power and Reliability,” ACM Transactions on Design Automation of Electronic Systems, Vol. 18, No. 3, Article 38, 23 pages, July 2013.
- J. Fang and S. S. Sapatnekar, “The Impact of BTI Variations on Timing in Digital Logic Circuits,” IEEE Transactions on Device and Material Reliability, Vol.13, No. 1, pp. 277-286, March 2013.
- S. Gupta and S. S. Sapatnekar, “Compact Current Source Models for Timing Analysis under Temperature and Body Bias Variations,” IEEE Transactions on VLSI Systems, Vol. 20, No. 11, pp. 2104 – 2117, November 2012.
- J. Fang and S. S. Sapatnekar, “Scalable Methods for Analyzing the Circuit Failure Probability Due to Gate Oxide Breakdown,” IEEE Transactions on VLSI Systems, Vol. 20, No. 11, pp. 1960 – 1973, November 2012.
- H. Qian, S. S. Sapatnekar, and E. Kursun, “Fast Poisson Solvers for Thermal Analysis,” ACM Transactions on Design Automation of Electronic Systems, Vol. 17, No. 3, Article 32, 23 pages, June 2012.
- J. Keane, C. H. Kim, Q. Liu, and S. S. Sapatnekar, “Process and Reliability Sensors for Nanoscale CMOS,” IEEE Design & Test, Vol. 29, No. 5, pp. 8 – 17, September/October 2012.
- P. Zhou, P.-H. Yuh, and S. S. Sapatnekar, “Optimized 3D Network-on-Chip Design Using Simulated Allocation,” ACM Transactions on Design Automation of Electronic Systems, Vol. 17, No. 2, Article 12, 19 pages, April 2012.
- S. S. Sapatnekar, “Overcoming Variations in Nanometer-Scale Technologies,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 1, No. 1, pp. 5–18, March 2011.
- S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, “Adaptive
Techniques for Overcoming Performance Degradation due to Aging in CMOS
Circuits,”
*IEEE Transactions on VLSI Systems*, Vol. 19, No. 4, pp. 603–614, January 2011. - Q. Liu and S. S. Sapatnekar, “Capturing Post-Silicon Variations
using a Representative Critical Path,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 29, No. 2, pp. 211 – 222, February 2010. - S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, “A Finite Oxide
Thickness Based Analytical Model for Negative Temperature Bias
Instability,”
*IEEE Transactions on Device and Material Reliability*, Vol. 9, No. 4, pp. 537 – 556, December 2009. - P. Zhou, K. Sridharan, and S. S. Sapatnekar, “Power Grid
Optimization in 3D Circuits Using MIMand CMOS Decoupling Capacitors,”
*IEEE Design & Test*, Vol. 26, No. 5, pp. 15 – 25, 2009. - P.-H. Yuh, S. S. Sapatnekar, C.-L. Yang, and Y.-W. Chang, “A
Progressive-ILP Based Routing Algorithm for the Synthesis of
Cross-Referencing Biochips,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 28, No. 9, pp. 1295 – 1306, September 2009. - Q. Liu and S. S. Sapatnekar, “A Framework for Scalable
Post-Silicon Statistical Delay Prediction under Spatial Variations,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 28, No. 8, pp. 1201 – 1212, August 2009. - H. D. Mogal, H. Qian, S. S. Sapatnekar, and K. Bazargan, “Fast and Accurate Statistical Criticality
Computation under Process Variations,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 28, No. 3, pp. 350 – 363, March 2009. - Y. Zhan, S. V. Kumar, and S. S. Sapatnekar, “Thermally-Aware Design,”
*Foundations and Trends in Electronic Design Automation*, Vol. 2, No. 3, pp. 255 – 370, 2008. - Y. Zhan and S. S. Sapatnekar, “Automated
Module Assignment in Stacked-Vdd Designs for High-Efficiency Power
Delivery,”
*ACM Journal on Emerging Technologies in Computing Systems*, Vol. 4, No. 4, Article 18, 20 pages, October 2008.

- S. S. Sapatnekar, “Variability
and Statistical Design,”
*IPSJ Transactions on System LSI Design Methodology*, Vol. 1, pp. 18 – 32, August 2008.

- J. Keane, H. Eom, T.-H. Kim, S. Sapatnekar, and C. Kim, “Stack Sizing for Optimal Current
Drivability in Subthreshold Circuits,”
*IEEE Transactions on VLSI Systems*, Vol. 16, No. 5, pp. 598 – 602, May 2008. - H. Qian and S. S. Sapatnekar, “Stochastic
Preconditioning for Diagonally Dominant Matrices,”
*SIAM Journal on Scientific Computing*, Vol. 30, No. 3, pp. 1178 – 1204, March 2008. - S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, “Body Bias Voltage Computations for Process
and Temperature Compensation,”
*IEEE Transactions on VLSI Systems*, Vol. 16, No. 3, pp. 249 – 262, March 2008.

- T. Zhang and S. S. Sapatnekar, “Buffering Global Interconnects in
Structured ASIC Design,”
*Integration: The VLSI Journal*, Vol. 41, No. 2, pp. 171 – 182, February 2008. - J. Gu, J. Keane, S. S. Sapatnekar, and C. H. Kim, “Statistical Leakage Estimation of Double
Gate FinFET Devices Considering the Width Quantization Property,”
*IEEE Transactions on VLSI Systems*, Vol. 16, No. 2, pp. 206 – 209, February 2008. - J. Singh, Z.-Q. Luo, and S. Sapatnekar, “A Geometric Programming-based Worst-Case
Gate Sizing Method Incorporating Spatial Correlation,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 27, No. 2, pp. 295 – 308, February 2008. - J. Singh and S. S. Sapatnekar, “A
Scalable Statistical Static Timing Analyzer Incorporating Correlated
Non-Gaussian and Gaussian Parameter Variations,”
*I**EEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 27, No. 1, pp. 160 – 173, January 2008. - S. K. Karandikar and S. S. Sapatnekar, “Technology Mapping Using Logical Effort
Solving the Load Distribution Problem,”
*I**EEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 27, No. 1, pp. 45 – 48, January 2008. - Y. Zhan and S. S. Sapatnekar, “High
Efficiency Green Function-Based Thermal Simulation Algorithms,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 26, No. 9, pp. 1661 – 1675, September 2007. - T. Zhang and S. S. Sapatnekar, “Simultaneous
Shield and Buffer Insertion for Crosstalk Noise Reduction in Global
Routing,”
*IEEE Transactions on VLSI Systems*, Vol. 15, No. 6, pp. 624 – 636, June 2007. - H. Chang and S. S. Sapatnekar, “Prediction
of Leakage Power under Process Uncertainties,”
*ACM Transactions on Design Automation of Electronic Systems*, Vol. 12, No. 2, Article 12 (27 pages), April 2007. - J.-L. Tsai, C. C.-P. Chen, G. Chen, B. Goplen, H. Qian, Y. Zhan,
S.-M. Kang, D.-F. Wong, and S. S. Sapatnekar, “Temperature-Aware Placement for SOCs,”
*Proceedings of the IEEE*, Vol. 94, No. 8, pp. 1502 - 1518, August 2006..

- C. J. Alpert, J. Hu, S. S. Sapatnekar, and C. N. Sze, “Accurate Estimation of Global Buffer Delay
within a Floorplan,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 25, No. 6, pp. 1140 – 1146, June 2006. - R. S. Shelar, P. Saxena, and S. S. Sapatnekar, “Technology Mapping Targeting Routing
Congestion Under Delay Constraints,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 25, No. 4, pp. 625 – 636, April 2006. - J. Singh and S. S. Sapatnekar, “A
Partition-based Algorithm for Power Grid Design using Locality,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 25, No. 4, pp. 664 – 677, April 2006. - B. Goplen and S. S. Sapatnekar, “Placement
of Thermal Vias in 3D ICs using Various Thermal Objectives,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 25, No. 4, pp. 692 – 709, April 2006.

- S. K. Karandikar and S. S. Sapatnekar, “Fast Comparisons of Circuit Implementations,”
*IEEE Transactions on VLSI Systems*, Vol. 13, No. 12, pp. 1329 – 1339, December 2005. - A. K. Sultania, D. Sylvester, and S. S. Sapatnekar, “Gate Oxide Leakage and Delay Tradeoffs for
Dual Tox Circuits,”
*IEEE Transactions on VLSI Systems*, Vol. 13, No. 12, pp. 1362 – 1375, December 2005. - C. Ababei, Y. Feng, B. Goplen, H. Mogal, T. Zhang, K. Bazargan,
and S. S. Sapatnekar, “Placement and
Routing in 3D Integrated Circuits,”
*IEEE Design & Test of Computers*, Vol. 22, No. 6, pp. 520 – 531, Nov – Dec 2005. - H. Chang and S. S. Sapatnekar, “Statistical
Timing Analysis Under Spatial Correlations,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 24, No. 9, pp. 1467 – 1482, September 2005. - R. S. Shelar and S. S. Sapatnekar, “BDD
Decomposition for Delay Oriented Pass Transistor Logic Synthesis,”
*IEEE Transactions on VLSI Systems*, Vol. 13, No. 8, pp. 957 – 970, August 2005. - H. Qian, S. R. Nassif, and S. S. Sapatnekar, “Power Grid Analysis using Random Walks,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 24, No. 8, pp. 1204 – 1224, August 2005. - R. S. Shelar, S. S. Sapatnekar, P. Saxena, and X. Wang, “A Predictive Distributed Congestion Metric
with Appication to Technology Mapping,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 24, No. 5, pp. 696 – 710, May 2005. - J. Singh and S. S. Sapatnekar, “Congestion-Aware
Topology Optimization of Structured Power/Ground Networks,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 24, No. 5, pp. 683 – 695, May 2005. - H. Qian, S. R. Nassif, and S. S. Sapatnekar, “Early-stage Power Grid Analysis for
Uncertain Working Modes,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 24, No. 5, pp. 676 – 682, May 2005. - H. Su, J. Hu, S. S. Sapatnekar, and S. R. Nassif, “A Methodology for the Simultaneous Design
of Supply and Signal Networks,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 23, No. 12, pp. 1614 – 1624, December 2004. - V. Sundararajan, S. S. Sapatnekar, and K. K. Parhi, “A New Approach for Integration of
Min-Area Retiming and Min-Delay Padding for Simultaneously Addressing
Short-path and Long-path Constraints,”
*ACM Transactions on Design Automation of Electronic Systems*, Vol. 9, No. 3, pp. 273 – 289, July 2004. - S. K. Karandikar and S. S. Sapatnekar, “Technology Mapping for SOI Domino Logic
Incorporating Solutions for the Parasitic Bipolar Effect,”
*IEEE Transactions on VLSI Systems*, Vol. 11, No. 9, pp. 1094 – 1105, December 2003. - H. Su, K. Gala, and S. S. Sapatnekar, “Analysis and Optimization of Structured
Power/Ground Networks,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 22, No. 11, pp. 1533 – 1544, November 2003.

- S. S. Sapatnekar and H. Su, “Analysis and Optimization of Power Grids,”
*IEEE Design and Test*(Special Issue on Power Supply and Analysis for IC's), Vol. 20, No. 3, pp. 7 – 15, May-June 2002. - C. J. Alpert, J. Hu, S. S. Sapatnekar, and P. Villarrubia, “A Practical Methodology for Early Buffer
and Wire Resource Allocation,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 22, No. 5, pp. 573 – 583, May 2003. - H. Su, S. S. Sapatnekar, and S. R. Nassif, “Optimal Decoupling Capacitor Sizing and
Placement for Standard Cell Layout Designs,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 22, No. 4, pp. 428 – 436, April 2003.

- H. Hu, D. T. Blaauw, V. Zolotov, K. Gala, M. Zhao, R. Panda, and
S. S. Sapatnekar, “Fast
On-Chip Inductance Simulation using a Precorrected-FFT Method,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 22, No. 1, pp. 49 – 61, January 2003. - H. Hu and S. S. Sapatnekar, “Efficient Inductance Extraction using
Circuit-Aware Techniques
*,*”*IEEE Transactions on VLSI Systems*, Vol. 10, No. 6, pp. 746 – 761, December 2002. - J. Hu and S. S. Sapatnekar, “A
Timing-constrained Simultaneous Global Routing Algorithm
*, “IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 21, No. 9, pp. 1025 – 1036, September 2002. - J. Pangjun and S. S. Sapatnekar, “Low
Power Clock Distribution using Multiple Voltages and Reduced Swings,”
*IEEE Transactions on VLSI Systems*, Vol. 10, No. 3, pp. 309 – 318, June 2002. - J. Hu and S. S. Sapatnekar, “Performance
Driven Global Routing Through Gradual Refinement,”
*VLSI Design*(Special Issue on Timing Analysis and Optimization for Deep Sub-Micron ICs), Vol. 15, No. 3, pp. 595 – 604, 2002. - V. Sundararajan, S. S. Sapatnekar, and K. K. Parhi, “Fast and Exact Transistor Sizing Based on
Iterative Relaxation,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 21, No. 5, pp. 568 – 581, May 2002. - S. Raman, S. S. Sapatnekar, and C. J. Alpert, “Probability-driven Routing in a
Datapath Environment,”
*Integration: The VLSI Journal*, Vol. 31, No. 2, pp. 159 – 182, May 2002. - M. Zhao and S. S. Sapatnekar, “Technology
Mapping Algorithms for Domino Logic,”
*ACM Transactions on Design Automation of Electronic Systems*, Vol. 7, No. 2, pp. 306 – 335, April 2002. - M. Zhao, R. V. Panda, S. S. Sapatnekar, and D. T. Blaauw, “Hierarchical Analysis of Power Distribution
Networks,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 21, No. 2, pp. 159 – 168, Feb 2002. - C. J. Alpert, M. Hrkic, J. Hu, A. B. Kahng, J. Lillis, B. Liu,
S. T. Quay, S. S. Sapatnekar, A. J. Sullivan, and P. Villarubia, “Buffered Steiner Trees for Difficult
Instances,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 21, No. 1, pp. 3 – 14, Jan 2002. - J. Hu and S. S. Sapatnekar, “A Survey on Multi-net Global Routing
for Integrated Circuits,”
*Integration: The VLSI Journal*, Vol. 31, No. 1, pp. 1 – 49, November 2001. - Y. Jiang, S. S. Sapatnekar and C. Bamji, “Technology Mapping for High Performance
Static CMOS and Pass Transistor Logic Designs,”
*IEEE Transactions on VLSI Systems*, Vol. 9, No. 5, pp. 577 – 589, October 2001. - M. Kuhlmann and S. S. Sapatnekar, “Exact
and Efficient Crosstalk Estimation,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 20, No. 7, pp. 858 – 866, July 2001. - C. J. Alpert, G. Gandham, J. Hu, J. L. Neves, S. T. Quay and S.
S. Sapatnekar, “A Steiner Tree
Construction for Buffers, Blockages and Bays,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 20, No. 4, pp. 556 – 562, April 2001. - M. Zhao and S. S. Sapatnekar, “Timing-driven
Partitioning and Timing Optimization of Mixed Static-Domino
Implementations,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 19, No. 11, pp. 1322 – 1336, November 2000. - K. Kasamsetty, M. Ketkar and S. S. Sapatnekar, “A New Class of Convex Functions for Delay
Modeling and their Application to the Transistor Sizing Problem,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 19, No. 7, pp. 779 – 788, July 2000. - S. S. Sapatnekar, “A Timing Model
Incorporating the Effect of Crosstalk on Delay and its Application to
Optimal Channel Routing,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 19, No. 5, pp. 550 – 559, May 2000. - J. Hu and S. S. Sapatnekar, “Algorithms
for Non-Hanan-based Optimization for VLSI Interconnect under a Higher
Order AWE Model,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 19, No. 4, pp. 446 – 458, April 2000. - S. S. Sapatnekar and W. Chuang, “Power-Delay
Optimizations in Gate Sizing,”
*ACM Transactions on Design Automation of Electronic Systems*, Vol. 5, No. 1, pp. 98 – 114, January 2000. - N. Maheshwari and S. S. Sapatnekar, “Optimizing Large Multiphase Level-Clocked
Circuits,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 18, No. 9, pp. 1249 – 1264, September 1999.

- N. Maheshwari and S. S. Sapatnekar, “Retiming Control Logic,”
*Integration: The VLSI Journal*, Vol. 28, No. 1, pp. 33 – 53, September 1999. - H. Hou, J. Hu and S. S. Sapatnekar, “NonHanan Routing,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 18, No. 4, pp. 436 – 444, April 1999. - Y. Jiang, S. S. Sapatnekar, C. Bamji and J. Kim, “Interleaving Buffer Insertion and
Transistor Sizing into a Single Optimization,”
*IEEE Transactions on VLSI Systems*, Vol. 6, No. 4, pp. 625 – 633, December 1998. - J. C. Shah, A. A. Younis, S. S. Sapatnekar and M. M. Hassoun, “An Algorithm for Simulating Power/Ground
Networks using Pade' Approximants and its Symbolic Implementation,”
*IEEE Transactions on Circuits and Systems II*, Vol. 45, No. 10, pp. 1372 – 1382, October 1998. - N. Maheshwari and S. S. Sapatnekar, “Efficient Retiming of Large Circuits,”
*IEEE Transactions on VLSI Systems*, Vol. 6, No. 1, pp. 74 – 83, March 1998. - H. Sathyamurthy, S. S. Sapatnekar, and J. P. Fishburn, “Speeding up Pipelined Circuits through a
Combination of Gate Sizing and Clock Skew Optimization
*,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 17, No. 2, pp. 173 – 182, February 1998. - D. Lehther and S. S. Sapatnekar, “Moment-Based
Techniques for RLC Clock Tree Construction,”
*IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing*, Vol. 45, No. 1, pp. 69 – 79, January 1998. - S. Ramaswamy, S. Sapatnekar, and P. Banerjee, “A Framework for Exploiting Data and
Functional Parallelism on Distributed Memory Multicomputers,”
*IEEE Transactions on Parallel and Distributed Systems*. Vol. 8, No. 11, pp. 1098 – 1116, November 1997 - S. S. Sapatnekar and R. B. Deokar, “Utilizing
the Retiming-Skew Equivalence in a Practical Algorithm for Retiming
Large Circuits,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*. Vol. 15, No. 10, pp. 1237 – 1248, October 1996. - P. K. Sancheti and S. S. Sapatnekar, “Optimal Design of Macrocells for Low Power
and High Speed,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*. Vol. 15, No. 9, pp. 1160 – 1166, September 1996. - S. S. Sapatnekar, “Wire Sizing as
a Convex Optimization Problem: Exploring the Area Delay Tradeoff,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 15, No. 8, pp. 1001 – 1011, August 1996. - W. Chuang, S. S. Sapatnekar, and I. N. Hajj, “Timing and Area Optimization for
Standard-Cell VLSI Circuit Design,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 14, No. 3, pp. 308 – 320, March 1995. - S. S. Sapatnekar, P. M. Vaidya, and S. M. Kang, “Convexity-based Algorithms for Design
Centering,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 13, No. 12, pp. 1536 – 1549, December 1994. - S. S. Sapatnekar, V. B. Rao, P. M. Vaidya, and S. M. Kang, “An Exact Solution to the Transistor Sizing
Problem for CMOS Circuits using Convex Optimization,”
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 12, No. 11, pp. 1621 – 1634, November 1993. - S. S. Sapatnekar and V. B. Rao, “A Transistor Sizing Tool for
CMOS Circuits,”
*Journal of Semicustom IC's*, Vol. 8, No. 2, pp. 39 – 44, 1990.

- J. Yin, P. Zhou, S. S. Sapatnekar, and A. Zhai, “Energy-Efficient Time-Division Multiplexed Hybrid-Switched NoC for Heterogeneous Multicore Systems,” Proceedings of the International Parallel and Distributed Processing Symposium, 2014 (to appear).
- B. Del Bel, J. Kim, C. H. Kim, and S. S. Sapatnekar, “Improving STT-MRAM Density Through Multibit Error Correction,” Proceedings of Design, Automation and Test in Europe, 2014.
- D. Sengupta and S. S. Sapatnekar, “Predicting Circuit Aging Using Ring Oscillators,” Proceedings of the Asia-South Pacific Design Automation Conference, 2014.
- A. Paul, C. Kshirsagar, S. Sapatnekar, S. Koester and C. Kim, “Leakage Modeling for Devices with Steep Sub-threshold Slope Considering Random Threshold Variations,” Proceedings of the International Conference on VLSI Design, 2014.
- A. Paul, D. Jiao, S. Sapatnekar, and C. H. Kim, “Deep Trench
Capacitor based Step-up and Step-down DC/DC Converters in 32nm SOI with
Opportunistic Current Borrowing and Fast DVFS Capabilities,” Proceedings of the IEEE Asian Solid-State Circuits Conference, 2013.

- S. Marella and S. S. Sapatnekar, “The Impact of Shallow Trench Isolation Effects on Circuit Performance,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013.
- V. Mishra and S. S. Sapatnekar, “The Impact of Electromigration in Copper Interconnects on Power Grid Integrity,” Proceedings of the ACM/EDAC/IEEE Design Automation Conference, 2013.
- S. S. Sapatnekar, “What happens when circuits grow old: Aging issues in CMOS design,” Proceedings of the International Symposium on VLSI Design, Automation & Test, 2013.
- P. Zhou, V. Mishra and S. S. Sapatnekar, “Placement Optimization of Power Supply Pads Based on Locality,” Proceedings of Design, Automation and Test in Europe, pp. 1665 – 1670, 2013.
- Y. Wei, Z. Li, C. Sze, S. Hu, C. J. Alpert, and S. S. Sapatnekar, “CATALYST: Planning Layer Directives for Effective Design Closure,” Proceedings of Design, Automation and Test in Europe, pp. 1873 – 1878, 2013.
- P. Zhou, W. H. Choi, B. Kim, C. H. Kim, and S. S. Sapatnekar, “Optimization of On-Chip Switched-Capacitor DC-DC Converters for High-Performance Applications,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 263 – 270, 2012.
- S. Marella, S. V. Kumar and S. S. Sapatnekar, “A Holistic Analysis of Circuit Timing Variations in 3D-ICs with Thermal and TSV-Induced Stress Considerations,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 317 – 324, 2012.
- J. Fang, S. Gupta, S. V. Kumar, S. K. Marella, V. Mishra, P. Zhou, and S. S. Sapatnekar, “Circuit Reliability: From Physics to Architectures,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 243 – 246, 2012.
- A. Paul, M. Amrein, S. Gupta, A. Vinod, A. Arun, S. Sapatnekar, and C. H. Kim, “Staggered Core Activation: A Circuit/Architectural Approach for Mitigating Resonant Supply Noise Issues in Multi-core Multi-power Domain Processors,” Proceedings of the IEEE Custom Integrated Circuits Conference, 2012.
- J. Yin, P. Zhou, A. Holey, S. S. Sapatnekar, and A. Zhai, “Energy-Efficient Non-Minimal Path Onchip Interconnection Network for Heterogeneous Systems,” Proceedings of the IEEE International Symposium on Low Power Electronics and Design, pp. 57 – 62, 2012.
- Y. Wei, C. Sze, N. Viswanathan, Z. Li, C. J. Alpert, L. Reddy, A. D. Huber, G. E. Tellez, D. Keller, S. S. Sapatnekar, “GLARE: Global and Local Wiring Aware Routability Evaluation,” Proceedings of the ACM/EDAC/IEEE Design Automation Conference, pp. 768 – 773, 2012.
- J. Fang and S. S. Sapatnekar, “Understanding the Impact of Transistor-Level BTI Variability,” Proceedings of the IEEE International Reliability Physics Symposium, pp. CR-2.1 – CR-2.6, 2012. (Best Poster Award)
- S. Gupta and S. S. Sapatnekar, “GNOMO: Greater-than-NOMinal Vdd Operation for BTI Mitigation,” Proceedings of the Asia-South Pacific Design Automation Conference, pp. 271 – 276, 2012.
- S. Gupta and S. S. Sapatnekar, “BTI-Aware Design Using Variable Latency Units,” Proceedings of the Asia-South Pacific Design Automation Conference, pp. 775 – 780, 2012.
- J. Fang and S. S. Sapatnekar, “The Impact of Hot Carriers on Timing in Large Circuits,” Proceedings of the Asia-South Pacific Design Automation Conference, pp. 591 – 596, 2012.

- B. Boghrati and S. S. Sapatnekar, “Incremental Power Network Analysis Using Backward Random Walks,” Proceedings of the Asia-South Pacific Design Automation Conference, pp. 41 – 46, 2012. (Nominated for Best Paper Award)
- Kumaraguruparan N., Sivaramakrishnan H., and S. S. Sapatnekar, “Residential Task Scheduling using the Multiple Knapsack Method,” Proceedings of the IEEE Innovative Smart Grid Technologies Conference, 2012.

- P. Zhou, D. Jiao, C. H. Kim, and S. S. Sapatnekar, “Exploration Of On-Chip Switched-Capacitor DC-DC Converter For Multicore Processors Using A Distributed Power Delivery Network,” Proceedings of the IEEE Custom Integrated Circuits Conference, 2011.
- P. Zhou, J. Yin, A. Zhai, and S. S. Sapatnekar, “NoC Frequency Scaling with Flexible-Pipeline Routers,” Proceedings of the IEEE International Symposium on Low Power Electronics and Design, pp. 403 – 408, 2011.

- J. Kung, I. Han, S. S. Sapatnekar, and Y. Shin, “Thermal Signature: A Simple Yet Accurate Thermal Index for Floorplan Optimization,” Proceedings of the ACM/EDAC/IEEE Design Automation Conference, pp. 108 – 113, 2011.

- B. Boghrati and S. S. Sapatnekar, “A Scaled Random Walk Solver for Fast Power Grid Analysis,” Proceedings of Design, Automation and Test in Europe, pp. 38 – 43, 2011.
- T. Kolpe, A. Zhai, and S. S. Sapatnekar, “Enabling Improved Power Management in Multicore Processors through Clustered DVFS,” Proceedings of Design, Automation and Test in Europe, pp. 293 – 298, 2011.
- J. Fang and S. S. Sapatnekar, “Accounting for Inherent Circuit Resilience and Process Variations in Analyzing Gate Oxide Reliability,” Proceedings of the Asia-South Pacific Design Automation Conference, pp. 689 – 694, 2011.
- H. Qian and S. S. Sapatnekar, “Fast Poisson Solvers for Thermal Analysis,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 698 – 702, 2010
- J. Fang and S. S. Sapatnekar, “Scalable Methods for the Analysis
and Optimization of Gate Oxide Breakdown,”
*Proceedings of the International Symposium on Quality Electronic Design*, pp. 638 – 645, 2010. (Best Paper Award) - Y. Wei and S. S. Sapatnekar, “Dummy Fill Optimization for
Enhanced Manufacturability,”
*Proceedings of the International Symposium on Physical Design*, pp. 97 – 104, 2010. - S. Gupta and S. S. Sapatnekar, “Current
Source Modeling in the Presence of Body Bias,”
*Proceedings of the Asia-South Pacific Design Automation Conference*, pp. 199 – 204, 2010. (Nominated for Best Paper Award) - P. Zhou, P.-H. Yuh, and S. S. Sapatnekar, “Application-Specific 3D Network-on-Chip
Design Using Simulated Allocation,”
*Proceedings of the Asia-South Pacific Design Automation Conference*, pp. 517 – 522, 2010. (Nominated for Best Paper Award) - Y. Wei, J. Hu, F. Liu, and S. S. Sapatnekar, “Physical Design Techniques for
Optimizing RTA-induced Variations,”
*Proceedings of the Asia-South Pacific Design Automation Conference*, pp. 745 – 750, 2010. - B. Boghrati and S. S. Sapatnekar, “Incremental Solution of Power Grids
using Random Walks,”
*Proceedings of the Asia-South Pacific Design Automation Conference*, pp. 757 – 762, 2010. (Nominated for Best Paper Award) - Q. Liu and S. S. Sapatnekar, “Synthesizing
a Representative Critical Path for Post-Silicon Delay Prediction,”
*Proceedings of the ACM International Symposium on Physical Design*, pp. 183 – 190, 2009 (Best paper award). - S. S. Sapatnekar, “Addressing
Thermal and Power Delivery Bottlenecks in 3D Circuits,”
*Proceedings of the Asia-South Pacific Design Automation Conference*, pp. 423 – 428, 2009. - S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, “Adaptive Techniques for Overcoming
Performance Degradation due to Aging in Digital Circuits,”
*Proceedings of the Asia-South Pacific Design Automation Conference*, pp. 284 – 289, 2009. - P. Zhou, K. Sridharan, and S. S. Sapatnekar, “Congestion-Aware Power Grid Optimization
for 3D Circuits Using MIM and CMOS Decoupling Capacitors,”
*Proceedings of the Asia-South Pacific Design Automation Conference*, pp. 179 – 184, 2009. - P. Zhou, J. Gu, P. Jain, C. H. Kim, and S. S. Sapatnekar, “Reliable Power Delivery for 3D ICs,”
*Sematech Workshop on Design and Test Challenges for 3D ICs*, 2008.

- P.-Y. Yuh, C.-L. Yang, Y.-W. Chang, and S. S. Sapatnekar, “A Progressive-ILP Based Routing Algorithm
for Cross-Referencing Biochips,”
*Proceedings of the ACM/IEEE Design Automation Conference*, pp. 284 – 289, 2008. - S. V. Kumar, C. Kashyap, and S. S. Sapatnekar, “A Framework for Block-Based Timing
Sensitivity Analysis,”
*Proceedings of the ACM/IEEE Design Automation Conference*, pp. 688 – 693, 2008. - S. V. Kumar, C. Kashyap, and S. S. Sapatnekar, “A Framework for
Block-Based Timing Sensitivity Analysis,”
*ACM Workshop on the Specification and Synthesis of Digital Systems (TAU)*, 2008. - H. Mogal, H. Qian, K. Bazargan, and S. S. Sapatnekar, “Clustering Based Pruning for Statistical
Criticality Computation under Process Variations,” P
*roceedings of the IEEE/ACM International Conference on Computer-Aided Design*, pp. 340 – 343, 2007. - D. Bufistov, J. Cortadella, M. Kishinevsky, and S. S. Sapatnekar,
“A General Model for Performance
Optimization of Sequential Systems,”
*Proceedings of the IEEE/ACM International Conference on Computer-Aided Design*, pp. 362 – 369, 2007. - Y. Zhan, T. Zhang, and S. S. Sapatnekar, “Module Assignment for Pin-Limited Designs
under the Stacked-Vdd Paradigm,”
*Proceedings of the IEEE/ACM International Conference on Computer-Aided Design*, pp. 656 – 659, 2007. - S. S. Sapatnekar, “CAD for 3D Circuits: Solutions and Challenges,” Proceedings of the VLSI/ULSI Multilevel Interconnection Conference, pp. 245 – 251, 2007 (Invited).
- B. Goplen and S. S. Sapatnekar, “Placement
of 3D ICs with Thermal and Interlayer Via Considerations,”
*Proceedings of the ACM/IEEE Design Automation Conference*, pp. 626 – 631, 2007.

- J. Gu, S. S. Sapatnekar, and C. H. Kim, “Width-dependent Statistical Leakage
Modeling for Random Dopant Induced Threshold Voltage Shift,”
*Proceedings of the ACM/IEEE Design Automation Conference*, pp. 87 – 92, 2007. (Nominated for Best Paper Award).

- S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, “NBTI-Aware Synthesis of Digital Circuits,”
*Proceedings of the ACM/IEEE Design Automation Conference*, pp. 370 – 375, 2007.

- Q. Liu and S. S. Sapatnekar, “Confidence
Scalable Post-Silicon Statistical Delay Prediction under Process
Variations,”
*Proceedings of the ACM/IEEE Design Automation Conference*, pp. 497 – 502, 2007.

- F. Marques, S. S. Sapatnekar, and A. I. Reis, “DAG Based Library-Free Technology
Mapping,”
*Proceedings of the Great Lakes Symposium on VLSI Systems*, pp. 293 – 298, 2007.

- Z. Li, C. J. Alpert, S. Quay, S. S. Sapatnekar and W. Shi, “Probabilistic Congestion Prediction with
Partial Blockages,”
*Proceedings of the International Symposium on Quality Electronic Design*, 2007.

- S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, “An Analytical Model for Negative Bias
Temperature Instability,”
*Proceedings of the IEEE/ACM International Conference on Computer-Aided Design*, pp. 493 – 496, 2006.

- V. Nookala, D. Lilja, and S. S. Sapatnekar, “Temperature-Aware Floorplanning of
Microarchitecture Blocks with IPC-Power Dependence Modeling and
Transient Analysis,”
*Proceedings of the IEEE International Symposium on Low Power Electronics and Design*, pp. 298 – 303, 2006.

- J. Gu, J. Keane, S. S. Sapatnekar, and C.-H. Kim, “Width
Quantization Aware FinFET Circuit Design,”
*Proceedings of the IEEE Custom Integrated Circuits Conference*, 2006. - J. Singh and S. S. Sapatnekar, “Statistical
Timing Analysis with Correlated Non-Gaussian Parameters using
Independent Component Analysis,”
*Proceedings of the ACM/IEEE Design Automation Conference*, pp. 155 – 160, 2006. - J. Keane, S. S. Sapatnekar, and C. H. Kim, “Subthreshold Logical Effort: A Systematic
Framework for Optimal Subthreshold Device Sizing,”
*Proceedings of the ACM/IEEE Design Automation Conference*, pp. 425 – 428, 2006. - S. S. Sapatnekar, “Physical Design
Automation Challenges for 3D ICs,”
*Proceedings of the International Conference on Integrated Circuit Design and Technology*, p. 172, 2006 (Invited paper). - H. Qian and S. S. Sapatnekar, “Stochastic
Preconditioning for Iterative Linear Equation Solvers,”
*Ninth Copper Mountain Conference on Iterative Methods*, 2006. - V. Nookala, D. J. Lilja, and S. S. Sapatnekar, “Comparing Simulation Techniques for
Microarchitecture-Aware Floorplanning,”
*IEEE International Symposium on Performance Analysis of Systems and Software*, pp. 80 – 88, 2006. - S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, “Impact of NBTI on SRAM Read Stability and
Design for Reliability,”
*Proceedings of the International Symposium on Quality Electronic Design*pp. 210 – 218, 2006. - Y. Zhan, B. Goplen, and S. S. Sapatnekar, “Electrothermal Analysis and Optimization
Techniques for Nanoscale Integrated Circuits,”
*Proceedings of the Asia-South Pacific Design Automation Conference*, pp. 219 – 222, 2006. - T. Zhang, Y. Zhan, and S. S. Sapatnekar, “Temperature-Aware Routing in 3D ICs,”
*Proceedings of the Asia-South Pacific Design Automation Conference*, pp. 309 – 314, 2006. - S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, “Mathematically-Assisted Adaptive Body
Bias (ABB) for Temperature Compensation in Gigascale LSI Systems,”
*Proceedings of the Asia-South Pacific Design Automation Conference*, pp. 559 – 564, 2006. - Y. Zhan, Y. Feng, and S. S. Sapatnekar, “A Fixed-die Floorplanning Algorithm
Using an Analytical Approach,”
*Proceedings of the Asia-South Pacific Design Automation Conference*, pp. 771 – 776, 2006. - Y. Zhan and S. S. Sapatnekar, “A
High Efficiency Full-Chip Thermal Simulation Algorithm,”
*Proceedings of the IEEE/ACM International Conference on Computer-Aided Design*, pp. 634 – 637, 2005. - H. Qian and S. S. Sapatnekar, “A
Hybrid Linear Equation Solver and its Application in Quadratic Placement,”
*Proceedings of the IEEE/ACM International Conference on Computer-Aided Design*, pp. 905 – 909, 2005. - F. R. Schneider, R. P. Ribas, S. S. Sapatnekar, and A. I. Reis, “Exact Lower Bound for the Number of
Switches in Series to Implement a Combinational Logic Cell,”
*Proceedings of the IEEE International Conference on Computer Desig*n, pp. 357 – 362, 2005. - B. Goplen, P. Saxena, and S. S. Sapatnekar, “Net Weighting to Reduce Repeater Counts
during Placement,”
*Proceedings of the ACM/IEEE Design Automation Conference*, pp. 503 – 508, 2005. - H. Chang and S. S. Sapatnekar, “Full-Chip
Analysis of Leakage Power Under Process Variations, Including Spatial
Correlations,”
*Proceedings of the ACM/IEEE Design Automation Conference*, pp. 523 – 528, 2005. - J. Singh, Z.-Q. Luo, and S. S. Sapatnekar, “Robust Gate Sizing by Geometric Programming,”
*Proceedings of the ACM/IEEE Design Automation Conference*, pp. 315 – 320, 2005. - V. Nookala, Y. Chen, D. J. Lilja, and S. S. Sapatnekar, “Microarchitecture-aware Floorplanning using
a Statistical Design of Experiments Approach,”
*Proceedings of the ACM/IEEE Design Automation Conference*, pp. 579 – 584, 2005. - V. Nookala and S. S. Sapatnekar, “Designing
Optimized Pipelined Global Interconnects: Algorithms and Methodology
Impact,”
*Proceedings of the IEEE International Symposium on Circuits and Systems*, pp. 608 – 611, 2005. - S. K. Karandikar and S. S. Sapatnekar, “Fast Estimation of Area-Delay Tradeoffs
in Circuit Sizing,”
*Proceedings of the IEEE International Symposium on Circuits and Systems*, pp. 3575 – 3578, 2005. - F. S. Marques, R. P. Ribas, S. S. Sapatnekar, and A. I. Reis, “A New Approach to the Use of
Satisfiability in False Path Detection,”
*Proceedings of the ACM Great Lakes Symposium on VLSI,*pp. 308 – 311, 2005. - J. Singh and S. S. Sapatnekar, “A
Fast Algorithm for Power Grid Design,”
*Proceedings of the ACM International Symposium on Physical Design*, pp. 70 – 77, 2005. - R. S. Shelar, P. Saxena, X. Wang, S. S. Sapatnekar, “A Near-optimal Technology Mapping
Algorithm Targeting Routing Congestion under Delay Constraints,”
*Proceedings of the ACM International Symposium on Physical Design*, pp. 137 – 144, 2005. - B. Goplen and S. S. Sapatnekar, “Thermal
Via Placement in 3D ICs,”
*Proceedings of the ACM International Symposium on Physical Design*, pp. 167 – 174, 2005. - Y. Zhan and S. S. Sapatnekar, “Fast
Computation of the Temperature Distribution in VLSI Chips Using the
Discrete Cosine Transform and Table Look-up,”
*Proceedings of the Asia/South Pacific Design Automation Conference*, 2005. - T. Zhang and S. S. Sapatnekar, “Buffering
Global Interconnects in Structured ASIC Design,”
*Proceedings of the Asia/South Pacific Design Automation Conference*, 2005. - H. Qian, J. Kozhaya, S. R. Nassif, and S. S. Sapatnekar, “A Chip-level Electrostatic Discharge
Simulation Strategy,”
*Proceedings of the IEEE/ACM International Conference on Computer-Aided Design*, pp. 315 – 318, 2004. - S. K. Karandikar and S. S. Sapatnekar, “Logical Effort Based Technology Mapping,”
*Proceedings of the IEEE/ACM International Conference on Computer-Aided Design*, pp. 419 – 422, 2004. - C. J. Alpert, J. Hu, S. S. Sapatnekar, and C.-N. Sze, “Accurate Estimation of Global Buffer
Delay within a Floorplan,”
*Proceedings of the IEEE/ACM International Conference on Computer-Aided Design*, pp. 706 – 711, 2004. - A. Sultania, D. Sylvester, and S. S. Sapatnekar, “Gate Oxide Leakage Reduction using
Transistor and Pin Reordering for Dual Tox Circuits,”
*Proceedings of the IEEE International Conference on Computer Design*, pp. 228 – 233, 2004. - T. Zhang and S. S. Sapatnekar, “Simultaneous
Shield and Buffer Insertion for Crosstalk Noise Reduction in Global
Routing,”
*Proceedings of the IEEE International Conference on Computer Design*, pp. 93 – 98, 2004. - H. Chang, H. Qian, and S. S. Sapatnekar, “The Certainty of Uncertainty: Randomness
in Nanometer Design,”
*Lecture Notes in Computer Science (Proceedings of PATMOS)*, E. Macii, V. Paliouras and O. Koufopavlou, ed., Vol. 3254, pp. 36 – 47, Springer, Berlin, Germany, 2004 (Invited Paper). - Y. Zhan, R. Harjani, and S. S. Sapatnekar, “On the Selection of On-Chip Inductors for
the Optimal VCO Design,”
*Proceedings of the IEEE Custom Integrated Circuits Conference*, 2004. - V. Nookala and S. S. Sapatnekar, “A
Method for Correcting the Functionality of a Wire-Pipelined Circuit,”
*Proceedings of the ACM/IEEE Design Automation Conference*, pp. 570 – 575, 2004 (Nominated for Best Paper Award). - A. Sultania, D. Sylvester, and S. S. Sapatnekar, “Tradeoffs between Gate Oxide Leakage and
Delay for Dual Tox Circuits,”
*Proceedings of the ACM/IEEE Design Automation Conference*, pp. 761 – 766, 2004. - J. Singh and S. S. Sapatnekar, “Topology
Optimization of Structured Power/Ground Networks,”
*Proceedings of the ACM International Symposium on Physical Design,*pp. 116 – 123, 2004. - H. Qian, S. R. Nassif, and S. S. Sapatnekar, “Early-stage Power Grid Analysis for
Uncertain Working Modes,”
*Proceedings of the ACM International Symposium on Physical Design*, pp. 132 – 137, 2004. - R. S. Shelar, S. S. Sapatnekar, P. Saxena, and X. Wang, “A Predictive Distributed Congestion and
its Application to Technology Mapping,”
*Proceedings of the ACM International Symposium on Physical Design*, pp. 210 – 217, 2004. - Y. Zhan and S. S. Sapatnekar, “Optimization
of Integrated Spiral Inductors Using Sequential Quadratic Programming,”
*Proceedings of**Design and Test in Europe*, 2004. - S. K. Karandikar and S. S. Sapatnekar, “Fast Comparison of Circuit Implementations,”
*Proceedings of Design and Test in Europe*, 2004. - C. Alpert, J. Hu, S. Sapatnekar, C-N. Sze, “A Fast Oracle for
Interconnect Delay Prediction,”
*Proceedings of the ACM Workshop on the Specication and Synthesis of Digital Systems (TAU)*, 2004. - H. Qian and S. S. Sapatnekar, “Hierarchical
random-walk algorithms for power grid analysis,”
*Proceedings of the Asian and South Pacific Design Automation Conference*, pp. 499-504, 2004.

- S. S. Sapatnekar, “High-performance
Power Grids for Nanometer Technology,”
*Proceedings of the International Conference on VLSI Design*, 2004 (Invited paper). - H. Chang and S. S. Sapatnekar, “Statistical
Timing Analysis Considering Spatial Correlations Using a Single
PERT-like Traversal,”
*Proceedings of the IEEE/ACM International Conference on Computer-Aided Design*, pp. 621 – 625, 2003. - B. Goplen and S. S. Sapatnekar, “Efficient
Thermal Placement of Standard Cells in 3D ICs using a Force Directed
Approach,”
*Proceedings of the IEEE/ACM International Conference on Computer-Aided Design*, pp. 86 – 89, 2003. - V. Rajappan and S. S. Sapatnekar, “An
Efficient Algorithm for Calculating the Worst-case Delay due to
Crosstalk,”
*Proceedings of the IEEE International Conference on Computer Design*, pp. 76 – 81, 2003.

- H. Qian, S. R. Nassif and S. S. Sapatnekar, “Random Walks in a Supply
Network,”
*Proceedings of the ACM/IEEE Design Automation Conference*, pp. 93 – 98, 2003 (Best paper award). - H. Hu, D. Blaauw, V. Zolotov, K. Gala, M. Zhao, R. Panda, and S.
Sapatnekar, “Table
Look-up Based Compact Modeling for On-chip Interconnect Timing and
Noise Analysis,”
*Proceedings of the IEEE International Symposium on Circuits and Systems*, 2003.

- G. Chen and S. S. Sapatnekar, “Partition-Driven Standard Cell Thermal
Placement,”
*Proceedings of the ACM International Symposium on Physical Design*, pp. 75 – 80, 2003.

- H. Hu, D. T. Blaauw, V. Zolotov, K. Gala, M. Zhao, R. Panda, and
S. S. Sapatnekar, “A
Precorrected-FFT Method for Simulating On-chip Inductance,”
*Proceedings of the IEEE/ACM International Conference on Computer-Aided Design*, pp. 221 – 227, 2002. - M. Ketkar and S. S. Sapatnekar, “Standby Power Optimization via Transistor
Sizing and Dual Threshold Voltage Assignment,”
*Proceedings of the IEEE/ACM International Conference on Computer-Aided Design*, pp. 375 – 378, 2002. - H. Hu and S. S. Sapatnekar, “Efficient PEEC-based Inductance Extraction
using Circuit-Aware Techniques,”
*Proceedings of the IEEE International Conference on Computer Design*, pp. 434 – 439, 2002. - H. Su, J. Hu, S. S. Sapatnekar, and S. R. Nassif, “Congestion-driven Codesign of Power and
Signal Networks,”
*Proceedings of the ACM/IEEE Design Automation Conference*, pp. 64 – 69, 2002. - R. Shelar and S. S. Sapatnekar, “Efficient
Layout Synthesis Algorithm for Pass Transistor Logic Circuits,”
*Workshop Notes of the International Workshop on Logic and Synthesis*, 2002. - H. Su, S. S. Sapatnekar, and S. R. Nassif, “An Algorithm for Optimal Decoupling
Capacitor Sizing and Placement for Standard Cell Layouts,”
*Proceedings of the ACM International Symposium on Physical Design*, pp. 68 – 73, 2002. - R. S. Shelar and S. S. Sapatnekar, “An Efficient Algorithm for Low Power Pass
Transistor Synthesis,”
*Proceedings of the International Conference on VLSI Design/Asia-South Pacific Design Automation Conference*, pp. 87 – 92, 2002. - H. Su and S. S. Sapatnekar, “Hybrid
Structured Clock Network Construction,”
*Proceedings of the IEEE/ACM International Conference on Computer-Aided Design*, pp. 333 – 336, 2001. - R. S. Shelar and S. S. Sapatnekar, “Recursive Bipartitioning of BDDs for
Performance Driven Synthesis of Pass Transistor Logic Circuits,”
*Proceedings of the IEEE/ACM International Conference on Computer-Aided Design*, pp. 449 – 452, 2001. - R. S. Shelar and S. S. Sapatnekar, “BDD
Decomposition for the Synthesis of High Performance PTL Circuits,”
*Workshop Notes of the International Workshop on Logic and Synthesis*, 2001. - J. Hu and S. S. Sapatnekar, “Performance
Driven Global Routing Through Gradual Refinement,”
*Proceedings of the IEEE International Conference on Computer Design*, pp. 481 – 483, 2001. - S. K. Karandikar and S. S. Sapatnekar, “Technology Mapping for SOI Domino Logic
Incorporating Solutions for the Parasitic Bipolar Effect,”
*Proceedings of the ACM/IEEE Design Automation Conference*, pp. 377 – 382, 2001. - M. Zhao and S. S. Sapatnekar, “A
New Structural Pattern Matching Algorithm for Technology Mapping,”
*Proceedings of the ACM/IEEE Design Automation Conference*, pp. 371 – 376, 2001 (Nominated for best paper award). - C. J. Alpert, J. Hu, S. S. Sapatnekar and P. Villarrubia, “A Practical Methodology for Early Buffer
and Wire Resource Allocation,”
*Proceedings of the ACM/IEEE Design Automation Conference*, pp. 189 – 194, 2001 (Best paper award). - H. Hu and S. Sapatnekar, “Circuit-Aware
On-Chip Inductance Extraction,”
*Proceedings of the IEEE Custom Integrated Circuits Conference*, pp. 245 – 248, 2001. - C. J. Alpert, G. Gandham, J. Hu, J. L. Neves, S. T. Quay and S.
S. Sapatnekar, “Steiner Tree Optimization
for Buffers, Blockages and Bays,”
*Proceedings of the IEEE International Symposium on Circuits and Systems*, 2001. - C. J. Alpert, G. Gandham, J. Hu, S. T. Quay, A. J. Sullivan, M.
Hrkic, J. Lillis, A. B. Kahng, B. Liu, S. S. Sapatnekar, “Buffered Steiner Trees for Difficult
Instances,”
*Proceedings of the ACM International Symposium on Physical Design*, pp. 4 – 9, 2001. - M. Ketkar, S. S. Sapatnekar, and P. Patra, “Convexity-Based Optimization for Power-Delay
Tradeoff using Transistor Sizing,”
*Proceedings of the IEEE/ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems*, pp. 52 – 57, 2000. - J. Hu and S. S. Sapatnekar, “A
Timing-constrained Algorithm for Simultaneous Routing of Multiple Nets,”
*Proceedings of the IEEE/ACM International Conference on Computer-Aided Design*, pp. 99 – 103, 2000. - H. Su, K. Gala and S. S. Sapatnekar, “Fast Analysis and Optimization of
Power/Ground Networks,”
*Proceedings of the IEEE/ACM International Conference on Computer-Aided Design*, pp. 477 – 480, 2000. - M. Ketkar, K. Kasamsetty and S. S. Sapatnekar, “Convex Delay Models for Transistor Sizing,”
*Proceedings of the ACM/IEEE Design Automation Conference*, pp. 655 – 660, 2000. - V. Sundararajan, S. S. Sapatnekar, K. K. Parhi, “MINFLOTRANSIT: Min-Cost Flow Based
Transistor Sizing Tool,”
*Proceedings of the ACM/IEEE Design Automation Conference*, pp. 649 – 654, 2000. - M. Zhao, R. V. Panda, S. S. Sapatnekar, T. Edwards, R. Chaudhry,
D. Blaauw, “Hierarchical Analysis of
Power Distribution Networks,”
*Proceedings of the ACM/IEEE Design Automation Conference*, pp. 150 – 155, 2000. - M. Zhao and S. S. Sapatnekar, “Dual-Monotonic
Domino Gate Mapping and Optimal Output Phase Assignment of Domino Logic,”
*Proceedings of the IEEE International Symposium on Circuits and Systems*, 2000. - S. Raman, S. S. Sapatnekar and C. J. Alpert, “Datapath Routing Based on a Decongestion
Metric,”
*Proceedings of the ACM International Symposium on Physical Design*, pp. 122 – 127, 2000. - S. S. Sapatnekar, “Capturing the
Effect of Crosstalk on Delay,”
*Proceedings of the 13th International Conference on VLSI Design*, pp. 364 – 369, 2000 (Invited Paper) . - S. S. Sapatnekar, “On the
Chicken-and-Egg Problem of Determining the Effect of Crosstalk on Delay
in Integrated Circuits,”
*Proceedings of the IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP-99)*, pp. 245 – 248, 1999 (Invited Paper) . - V. Sundararajan, S. S. Sapatnekar and K. K. Parhi, “MARSH: Minimum Area Retiming with Setup
and Hold Constraints,”
*Proceedings of the IEEE International Conference on Computer-Aided Design*, pp. 2 – 6, 1999. - M. Zhao and S. S. Sapatnekar, “Timing-driven
Partitioning for Two-Phase Domino and Mixed Static/Domino
Implementations,”
*Proceedings of the IEEE International Conference on Computer-Aided Design*, pp. 102 – 105, 1999. - Y. Jiang and S. S. Sapatnekar, “An
Integrated Algorithm for Combined Placement and Libraryless Technology
Mapping,”
*Proceedings of the IEEE International Conference on Computer-Aided Design*, pp. 107 – 110, 1999. - M. Kuhlmann, S. S. Sapatnekar and K. K. Parhi, “Efficient Crosstalk Estimation,”
*Proceedings of the IEEE International Conference on Computer Design*, pp. 266 – 272, 1999. - J. Pangjun and S. S. Sapatnekar, “Clock
Distribution using Multiple Voltages,”
*Proceedings of the ACM International Symposium on Low Power Electronics and Design*, pp. 145-150, 1999. - J. Hu and S. S. Sapatnekar, “FAR-DS:
Full-plane AWE Routing with Driver Sizing,”
*Proceedings of the ACM/IEEE Design Automation Conference*, pp. 84 – 89, 1999. - J. Hu and S. S. Sapatnekar, “Simultaneous
Buffer Insertion and Non-Hanan Optimization for VLSI Interconnect under
a Higher Order AWE Model,”
*Proceedings of the ACM International Symposium on Physical Design*, pp. 133 – 138, 1999. - M. Zhao and S. S. Sapatnekar, “Technology
Mapping for Domino Logic,”
*Proceedings of the IEEE International Conference on Computer-Aided Design*, pp. 248 – 251, 1998. - Y. Jiang, S. S. Sapatnekar and C. Bamji, “A Fast Global Gate Collapsing Technique for
High Performance Designs Using Static CMOS and Pass Transistor Logic,”
*Proceedings of the IEEE International Conference on Computer Design*, pp. 276 – 281, 1998 (Best paper award). - M. Zhao and S. S. Sapatnekar, “Timing
Optimization of Mixed Static and Domino Logic,”
*Proceedings of the IEEE International Symposium on Circuits and Systems*, 1998. - H. Hou and S. S. Sapatnekar, “Routing
Tree Topology Construction to Meet Interconnect Timing Constraints,”
*Proceedings of the ACM International Symposium on Physical Design*, pp. 205 – 210, 1998. - Y. Jiang, S. S. Sapatnekar, C. Bamji and J. Kim, “Combined Transistor Sizing with Buffer
Insertion for Timing Optimization,”
*Proceedings of the IEEE Custom Integrated Circuits Conference*, pp. 605 – 608, 1998. - N. Maheshwari and S. S. Sapatnekar, “Efficient
Minarea Retiming of Large Level-clocked Circuits,”
*Proceedings of the Design Automation and Test in Europe (DATE) Conference*, pp. 840 – 845, 1998. - N. Maheshwari and S. S. Sapatnekar, “Retiming
Level-clocked Circuits for Latch Count Minimization,”
*Proceedings of the ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems*, pp. 135 – 140, 1997. - N. Maheshwari and S. S. Sapatnekar, “Minimum Area Retiming with Equivalent
Initial States,”
*Proceedings of the IEEE/ACM International Conference on Computer-aided Design*, pp. 216 – 219, 1997. - N. Maheshwari and S. S. Sapatnekar, “An
Improved Algorithm for Minimum Area Retiming,”
*Proceedings of the ACM/IEEE Design Automation Conference*, pp. 2 – 6, 1997 (Best paper award). - S. Pilli and S. S. Sapatnekar, “Power
Estimation Considering Statistical IC Parameter Variations,”
*Proceedings of the IEEE International Symposium on Circuits and Systems*, pp. 1524 – 1527, 1997. - J. C. Shah, A. A. Younis, S. S. Sapatnekar and M. M. Hassoun, “Symbolic Analysis of Power/Ground Networks
using Moment-matching Methods,”
*Proceedings of the European Conference on Circuit Theory and Design*, pp. 1292 – 1297, 1997. - J. Kim, C. Bamji, Y. Jiang and S. S. Sapatnekar, “Concurrent Transistor Sizing and Buffer
Insertion by Considering Cost-Delay Tradeoffs,”
*Proceedings of the International Symposium on Physical Design*, pp. 130 – 135, 1997. - D. Lehther and S. S. Sapatnekar, “Clock
Tree Synthesis for Multi-Chip Modules,”
*Proceedings of the IEEE/ACM International Conference on Computer-Aided Design*, pp. 53 – 56, 1996. - N. Maheshwari and S. S. Sapatnekar, “A
Practical Algorithm for Retiming Level-Clocked Circuits,”
*Proceedings of the IEEE International Conference on Computer Design*, pp. 440 – 445, 1996. - S. S. Sapatnekar, J. Shah and M. M. Hassoun, “Application of Symbolic Analysis to Power
and Ground Interconnect Optimization,”
*Proceedings of the 4th International Workshop on Symbolic Methods and Applications to Circuit Design*, 1996. - S. S. Sapatnekar, “Efficient
Calculation of All-Pairs Input-to-Output Delays in Synchronous
Sequential Circuits,”
*Proceedings of the IEEE International Symposium on Circuits and Systems*, pp. IV-520 – IV-523, 1996. - J. C. Shah and S. S. Sapatnekar, “Wiresizing
with Buffer Placement and Sizing for Power-Delay Tradeoffs,”
*Proceedings of VLSI Design-96*, pp. 346 – 351, 1996. - S. S. Sapatnekar and W. Chuang, “Power
vs. Delay in Gate Sizing: Conflicting Objectives?”
*Proceedings of the IEEE/ACM International Conference on Computer-Aided Design*, pp. 463 – 466, 1995. - H. Sathyamurthy, S. S. Sapatnekar, and J. P. Fishburn, “Speeding up Pipelined Circuits through a
Combination of Gate Sizing and Clock Skew Optimization,”
*Proceedings of the IEEE/ACM International Conference on Computer-Aided Design*, pp. 467 – 470, 1995. - N. Maheshwari and S. S. Sapatnekar, “Gate Size
Optimization for Row-based Layouts,”
*Proceedings of the 38th Midwest Symposium on Circuits and Systems*, 1995. - R. B. Deokar and S. S. Sapatnekar, “A
Fresh Look at Retiming via Clock Skew Optimization,”
*Proceedings of the ACM/IEEE Design Automation Conference*, pp. 304 – 309, 1995. - P. K. Sancheti and S. S. Sapatnekar, “Layout Optimization Using Arbitrarily High
Degree Posynomials,”
*Proceedings of the IEEE International Symposium on Circuits and Systems*, pp. 53 – 56, 1995. - S. S. Sapatnekar, “RC Interconnect
Optimization under the Elmore Delay Model,”
*Proceedings of the ACM/IEEE Design Automation Conference*, pp. 387 – 391, 1994. - P. K. Sancheti and S. S. Sapatnekar, “Interconnect Design Using Convex Optimization,”
*Proceedings of the IEEE Custom Integrated Circuits Conference*, pp. 549 – 552, 1994. [No figures in PS file] - R. B. Deokar and S. S. Sapatnekar, “A
Graph-theoretic Approach to Clock Skew Optimization,”
*Proceedings of the IEEE International Symposium on Circuits and Systems*, pp. 1.407 – 1.410, 1994. - J. Kim, S. M. Kang, and S. S. Sapatnekar, “High-Performance CMOS
Macromodule Layout Synthesis,”
*Proceedings of the IEEE International Symposium on Circuits and Systems*, pp. 4.179 – 4.182, 1994. - S. Ramaswamy, S. Sapatnekar, and P. Banerjee, “A Convex Programming Approach for
Exploiting Data and Functional Parallelism on Distributed Memory
Multicomputers,”
*Proceedings of the International Conference on Parallel Processing*, pp. 116 – 125, 1994. - W. Chuang, S. S. Sapatnekar, and I. N. Hajj, “A Unified Algorithm for Gate Sizing and
Clock Skew Optimization to Minimize Sequential Circuit Area,”
*Proceedings of the IEEE/ACM International Conference on Computer-Aided Design*, pp. 220 – 223, 1993. - S. S. Sapatnekar, P. M. Vaidya, and S. M. Kang, “Convexity-based Algorithms for Design
Centering,”
*Proceedings of the IEEE/ACM International Conference on Computer-Aided Design*, pp. 206 – 209, 1993. - S. S. Sapatnekar, P. M. Vaidya, and S. M. Kang, “Feasible Region Approximation Using Convex
Polytopes,”
*Proceedings of the IEEE International Symposium on Circuits and Systems*, pp. 1786 – 1789, 1993. [No figures in pdf file] - W. Chuang, S. S. Sapatnekar, and I. N. Hajj, “Delay and Area Optimization for Discrete
Gate Sizes under Double-Sided Timing Constraints,”
*Proceedings of the IEEE Custom Integrated Circuits Conference*, pp. 9.4.1 – 9.4.4, 1993. - S. S. Sapatnekar and V. B. Rao, “A Convex Optimization Approach
to Transistor Sizing for CMOS Circuits,” Invited paper at the
*ORSA/TIMS 34th Joint National Meeting*, 1992. - R. W. Thaik, S. S. Sapatnekar, and S. M. Kang, “iCGEN: A CMOS
Integrated Circuit Layout Generator,”
*Proceedings of the International Workshop on Layout Synthesis*, 1992. - S. S. Sapatnekar, V. B. Rao, and P. M. Vaidya, “A Convex
Optimization Approach to Transistor Sizing for CMOS Circuits,”
*Proceedings of the IEEE International Conference on Computer-Aided Design*, pp. 482 – 485, 1991. - S. S. Sapatnekar and V. B. Rao, “iDEAS: A Delay Estimator and
Transistor Sizing Tool for CMOS Circuits,”
*Proceedings of the IEEE Custom Integrated Circuits Conference*, pp. 9.3.1 – 9.3.4, 1990.