List of Publications

Last updated January 2009

Many of the papers below have been made available in PDF format as a courtesy. Please be aware that almost every paper listed below is copyrighted by the organization responsible for the corresponding conference or journal.

Books

  1. C. J. Alpert, D. P. Mehta, and S. S. Sapatnekar, editors, Handbook of Algorithms for VLSI Physical Design Automation, CRC Press, New York, NY, 2008.
  2. P. Saxena, R. S. Shelar, and S. S. Sapatnekar, Routing Congestion in VLSI Circuits, Springer, Boston, MA, 2007.
  3. D. J. Lilja and S. S. Sapatnekar, Designing Digital Computing Systems with Verilog, Cambridge University Press, Cambridge, UK, 2005.
  4. S. S. Sapatnekar, Timing, Kluwer Academic Publishers, Boston, MA, 2004.
  5. B. Lu, D.-Z. Du, and S. S. Sapatnekar, editors, Layout Optimization in VLSI Design, Kluwer Academic Publishers, Boston, MA, 2001.
  6. N. Maheshwari and S. S. Sapatnekar, Timing Analysis and Optimization of Sequential Circuits, Kluwer Academic Publishers, Boston, MA, 1999.
  7. S. S. Sapatnekar and S. M. Kang, Design Automation for Timing-Driven Layout Synthesis, Kluwer Academic Publishers, Boston, MA, 1993.

Book Chapters

  1. S. S. Sapatnekar, “Computer-Aided Design for 3D Circuits,” in 3D IC Integration: Technology and Applications, P. Ramm, C. Bower, P. Garrou, eds., Wiley-VCH, Weinheim, Germany, 2008.
  2. K. Bazargan and S. S. Sapatnekar, “Physical Design for 3D Circuits,” in The Handbook of Algorithms for VLSI Physical Design Automation, C. J. Alpert, D. P. Mehta, and S. S. Sapatnekar, eds., CRC Press, 2008.
  3. F. Liu and S. S. Sapatnekar, “Metrics Used in Physical Design,” in The Handbook of Algorithms for VLSI Physical Design Automation, C. J. Alpert, D. P. Mehta, and S. S. Sapatnekar, eds., CRC Press, 2008.
  4. S. S. Sapatnekar, “Static Timing Analysis,” in The CRC Handbook of EDA for IC Design, L. Scheffer, L. Lavagno, and G. Martin, eds., pp. 6-1 . 6-17, CRC Press, Boca Raton, FL, 2006.
  5. S. S. Sapatnekar, “Convex Optimization,” in The Wiley Encyclopedia of Computer Science and Engineering, J. G. Webster, ed., John Wiley and Sons, New York, NY (in press).
  6. J. Hu and S. S. Sapatnekar, “Non-Hanan Optimization for Global VLSI Interconnect,” in Layout Optimizations in VLSI Design, B. Lu, D.-Z. Du, and S. S. Sapatnekar, ed., Kluwer Academic Publishers, Boston, MA, 2001.
  7. S. S. Sapatnekar, “Circuit Optimization,” in The Wiley Encyclopedia of Electrical and Electronics Engineering, J. G. Webster, ed., John Wiley and Sons, New York, NY, 2001.
  8. S. S. Sapatnekar, “Convex Optimization,” in The Wiley Encyclopedia of Electrical and Electronics Engineering, J. G. Webster, ed., Vol. 4, John Wiley, New York, NY, 1999.
  9. S. S. Sapatnekar, “Design by Optimization,” in The Circuits and Filters Handbook, ed. W.-K. Chen, CRC Press, 1995.

Journal Publications

  1. H. D. Mogal, H. Qian, S. S. Sapatnekar, and K. Bazargan, “Fast and Accurate Statistical Criticality Computation under Process Variations,” accepted for publication in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008.
  2. Y. Zhan, S. V. Kumar, and S. S. Sapatnekar, “Thermally-Aware Design,” Foundations and Trends in Electronic Design Automation, Vol. 2, No. 3, pp. 255 – 370, 2008.
  3. Y. Zhan and S. S. Sapatnekar, “Automated Module Assignment in Stacked-Vdd Designs for High-Efficiency Power Delivery,”ACM Journal on Emerging Technologies in Computing Systems, Vol. 4, No. 4, Article 18, 20 pages, October 2008.
  4. S. S. Sapatnekar, “Variability and Statistical Design,” IPSJ Transactions on System LSI Design Methodology, Vol. 1, pp. 18 – 32, August 2008.
  5. J. Keane, H. Eom, T.-H. Kim, S. Sapatnekar, and C. Kim, “Stack Sizing for Optimal Current Drivability in Subthreshold Circuits,” IEEE Transactions on VLSI Systems, Vol. 16, No. 5, pp. 598 –– 602, May 2008.
  6. H. Qian and S. S. Sapatnekar, “Stochastic Preconditioning for Diagonally Dominant Matrices,” SIAM Journal on Scientific Computing, Vol. 30, No. 3, pp. 1178 –– 1204, March 2008.
  7. S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, “Body Bias Voltage Computations for Process and Temperature Compensation,” IEEE Transactions on VLSI Systems, Vol. 16, No. 3, pp. 249 – 262, March 2008.
  8. T. Zhang and S. S. Sapatnekar, “Buffering Global Interconnects in Structured ASIC Design,” Integration: The VLSI Journal, Vol. 41, No. 2, pp. 171 – 182, February 2008.
  9. J. Gu, J. Keane, S. S. Sapatnekar, and C. H. Kim, “Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization Property,” IEEE Transactions on VLSI Systems, Vol. 16, No. 2, pp. 206 – 209, February 2008.
  10. J. Singh, Z.-Q. Luo, and S. Sapatnekar, “A Geometric Programming-based Worst-Case Gate Sizing Method Incorporating Spatial Correlation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 2, pp. 295 – 308, February 2008.
  11. J. Singh and S. S. Sapatnekar, “A Scalable Statistical Static Timing Analyzer Incorporating Correlated Non-Gaussian and Gaussian Parameter Variations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 1, pp. 160 – 173, January 2008.
  12. S. K. Karandikar and S. S. Sapatnekar, “Technology Mapping Using Logical Effort Solving the Load Distribution Problem,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 1, pp. 45 – 48, January 2008.
  13. Y. Zhan and S. S. Sapatnekar, “High Efficiency Green Function-Based Thermal Simulation Algorithms,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No. 9, pp. 1661 – 1675, September 2007.
  14. T. Zhang and S. S. Sapatnekar, “Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing,” IEEE Transactions on VLSI Systems, Vol. 15, No. 6, pp. 624 – 636, June 2007.
  15. H. Chang and S. S. Sapatnekar, “Prediction of Leakage Power under Process Uncertainties,” ACM Transactions on Design Automation of Electronic Systems, Vol. 12, No. 2, Article 12 (27 pages), April 2007.
  16. J.-L. Tsai, C. C.-P. Chen, G. Chen, B. Goplen, H. Qian, Y. Zhan, S.-M. Kang, D.-F. Wong, and S. S. Sapatnekar, “Temperature-Aware Placement for SOCs,” Proceedings of the IEEE, Vol. 94, No. 8, pp. 1502 - 1518, August 2006..
  17. C. J. Alpert, J. Hu, S. S. Sapatnekar, and C. N. Sze, “Accurate Estimation of Global Buffer Delay within a Floorplan,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, No. 6, pp. 1140 – 1146, June 2006.
  18. R. S. Shelar, P. Saxena, and S. S. Sapatnekar, “Technology Mapping Targeting Routing Congestion Under Delay Constraints,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, No. 4, pp. 625 – 636, April 2006.
  19. J. Singh and S. S. Sapatnekar, “A Partition-based Algorithm for Power Grid Design using Locality,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, No. 4, pp. 664 – 677, April 2006.
  20. B. Goplen and S. S. Sapatnekar, “Placement of Thermal Vias in 3D ICs using Various Thermal Objectives,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, No. 4, pp. 692 – 709, April 2006.
  21. S. K. Karandikar and S. S. Sapatnekar, “Fast Comparisons of Circuit Implementations,” IEEE Transactions on VLSI Systems, Vol. 13, No. 12, pp. 1329 – 1339, December 2005.
  22. A. K. Sultania, D. Sylvester, and S. S. Sapatnekar, “Gate Oxide Leakage and Delay Tradeoffs for Dual Tox Circuits,” IEEE Transactions on VLSI Systems, Vol. 13, No. 12, pp. 1362 – 1375, December 2005.
  23. C. Ababei, Y. Feng, B. Goplen, H. Mogal, T. Zhang, K. Bazargan, and S. S. Sapatnekar, “Placement and Routing in 3D Integrated Circuits,” IEEE Design & Test of Computers, Vol. 22, No. 6, pp. 520 – 531, Nov – Dec 2005.
  24. H. Chang and S. S. Sapatnekar, “Statistical Timing Analysis Under Spatial Correlations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 9, pp. 1467 – 1482, September 2005.
  25. R. S. Shelar and S. S. Sapatnekar, “BDD Decomposition for Delay Oriented Pass Transistor Logic Synthesis,” IEEE Transactions on VLSI Systems, Vol. 13, No. 8, pp. 957 – 970, August 2005.
  26. H. Qian, S. R. Nassif, and S. S. Sapatnekar, “Power Grid Analysis using Random Walks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 8, pp. 1204 – 1224, August 2005.
  27. R. S. Shelar, S. S. Sapatnekar, P. Saxena, and X. Wang, “A Predictive Distributed Congestion Metric with Appication to Technology Mapping,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 5, pp. 696 – 710, May 2005.
  28. J. Singh and S. S. Sapatnekar, “Congestion-Aware Topology Optimization of Structured Power/Ground Networks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 5, pp. 683 – 695, May 2005.
  29. H. Qian, S. R. Nassif, and S. S. Sapatnekar, “Early-stage Power Grid Analysis for Uncertain Working Modes,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 5, pp. 676 – 682, May 2005.
  30. H. Su, J. Hu, S. S. Sapatnekar, and S. R. Nassif, “A Methodology for the Simultaneous Design of Supply and Signal Networks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, No. 12, pp. 1614 – 1624, December 2004.
  31. V. Sundararajan, S. S. Sapatnekar, and K. K. Parhi, “A New Approach for Integration of Min-Area Retiming and Min-Delay Padding for Simultaneously Addressing Short-path and Long-path Constraints,” ACM Transactions on Design Automation of Electronic Systems, Vol. 9, No. 3, pp. 273 – 289, July 2004.
  32. S. K. Karandikar and S. S. Sapatnekar, “Technology Mapping for SOI Domino Logic Incorporating Solutions for the Parasitic Bipolar Effect,” IEEE Transactions on VLSI Systems, Vol. 11, No. 9, pp. 1094 – 1105, December 2003.
  33. H. Su, K. Gala, and S. S. Sapatnekar, “Analysis and Optimization of Structured Power/Ground Networks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 11, pp. 1533 – 1544, November 2003.
  34. S. S. Sapatnekar and H. Su, “Analysis and Optimization of Power Grids,” IEEE Design and Test (Special Issue on Power Supply and Analysis for IC's), Vol. 20, No. 3, pp. 7 – 15, May-June 2002.
  35. C. J. Alpert, J. Hu, S. S. Sapatnekar, and P. Villarrubia, “A Practical Methodology for Early Buffer and Wire Resource Allocation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 5, pp. 573 – 583, May 2003.
  36. H. Su, S. S. Sapatnekar, and S. R. Nassif, “Optimal Decoupling Capacitor Sizing and Placement for Standard Cell Layout Designs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 4, pp. 428 – 436, April 2003.
  37. H. Hu, D. T. Blaauw, V. Zolotov, K. Gala, M. Zhao, R. Panda, and S. S. Sapatnekar, “Fast On-Chip Inductance Simulation using a Precorrected-FFT Method,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 1, pp. 49 – 61, January 2003.
  38. H. Hu and S. S. Sapatnekar, “Efficient Inductance Extraction using Circuit-Aware Techniques,” IEEE Transactions on VLSI Systems, Vol. 10, No. 6, pp. 746 – 761, December 2002.
  39. J. Hu and S. S. Sapatnekar, “A Timing-constrained Simultaneous Global Routing Algorithm, “IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 9, pp. 1025 – 1036, September 2002.
  40. J. Pangjun and S. S. Sapatnekar, “Low Power Clock Distribution using Multiple Voltages and Reduced Swings,” IEEE Transactions on VLSI Systems, Vol. 10, No. 3, pp. 309 – 318, June 2002.
  41. J. Hu and S. S. Sapatnekar, “Performance Driven Global Routing Through Gradual Refinement,” VLSI Design (Special Issue on Timing Analysis and Optimization for Deep Sub-Micron ICs), Vol. 15, No. 3, pp. 595 – 604, 2002.
  42. V. Sundararajan, S. S. Sapatnekar, and K. K. Parhi, “Fast and Exact Transistor Sizing Based on Iterative Relaxation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 5, pp. 568 – 581, May 2002.
  43. S. Raman, S. S. Sapatnekar, and C. J. Alpert, “Probability-driven Routing in a Datapath Environment,” Integration: The VLSI Journal, Vol. 31, No. 2, pp. 159 – 182, May 2002.
  44. M. Zhao and S. S. Sapatnekar, “Technology Mapping Algorithms for Domino Logic,” ACM Transactions on Design Automation of Electronic Systems, Vol. 7, No. 2, pp. 306 – 335, April 2002.
  45. M. Zhao, R. V. Panda, S. S. Sapatnekar, and D. T. Blaauw, “Hierarchical Analysis of Power Distribution Networks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 2, pp. 159 – 168, Feb 2002.
  46. C. J. Alpert, M. Hrkic, J. Hu, A. B. Kahng, J. Lillis, B. Liu, S. T. Quay, S. S. Sapatnekar, A. J. Sullivan, and P. Villarubia, “Buffered Steiner Trees for Difficult Instances,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 1, pp. 3 – 14, Jan 2002.
  47. J. Hu and S. S. Sapatnekar, “A Survey on Multi-net Global Routing for Integrated Circuits,” Integration: The VLSI Journal, Vol. 31, No. 1, pp. 1 – 49, November 2001.
  48. Y. Jiang, S. S. Sapatnekar and C. Bamji, “Technology Mapping for High Performance Static CMOS and Pass Transistor Logic Designs,” IEEE Transactions on VLSI Systems, Vol. 9, No. 5, pp. 577 – 589, October 2001.
  49. M. Kuhlmann and S. S. Sapatnekar, “Exact and Efficient Crosstalk Estimation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, No. 7, pp. 858 – 866, July 2001.
  50. C. J. Alpert, G. Gandham, J. Hu, J. L. Neves, S. T. Quay and S. S. Sapatnekar, “A Steiner Tree Construction for Buffers, Blockages and Bays,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, No. 4, pp. 556 – 562, April 2001.
  51. M. Zhao and S. S. Sapatnekar, “Timing-driven Partitioning and Timing Optimization of Mixed Static-Domino Implementations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 19, No. 11, pp. 1322 – 1336, November 2000.
  52. K. Kasamsetty, M. Ketkar and S. S. Sapatnekar, “A New Class of Convex Functions for Delay Modeling and their Application to the Transistor Sizing Problem,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 19, No. 7, pp. 779 – 788, July 2000.
  53. S. S. Sapatnekar, “A Timing Model Incorporating the Effect of Crosstalk on Delay and its Application to Optimal Channel Routing,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 19, No. 5, pp. 550 – 559, May 2000.
  54. J. Hu and S. S. Sapatnekar, “Algorithms for Non-Hanan-based Optimization for VLSI Interconnect under a Higher Order AWE Model,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 19, No. 4, pp. 446 – 458, April 2000.
  55. S. S. Sapatnekar and W. Chuang, “Power-Delay Optimizations in Gate Sizing,” ACM Transactions on Design Automation of Electronic Systems, Vol. 5, No. 1, pp. 98 – 114, January 2000.
  56. N. Maheshwari and S. S. Sapatnekar, “Optimizing Large Multiphase Level-Clocked Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, No. 9, pp. 1249 – 1264, September 1999.
  57. N. Maheshwari and S. S. Sapatnekar, “Retiming Control Logic,” Integration: The VLSI Journal, Vol. 28, No. 1, pp. 33 – 53, September 1999.
  58. H. Hou, J. Hu and S. S. Sapatnekar, “NonHanan Routing,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, No. 4, pp. 436 – 444, April 1999.
  59. Y. Jiang, S. S. Sapatnekar, C. Bamji and J. Kim, “Interleaving Buffer Insertion and Transistor Sizing into a Single Optimization,” IEEE Transactions on VLSI Systems, Vol. 6, No. 4, pp. 625 – 633, December 1998.
  60. J. C. Shah, A. A. Younis, S. S. Sapatnekar and M. M. Hassoun, “An Algorithm for Simulating Power/Ground Networks using Pade' Approximants and its Symbolic Implementation,” IEEE Transactions on Circuits and Systems II, Vol. 45, No. 10, pp. 1372 – 1382, October 1998.
  61. N. Maheshwari and S. S. Sapatnekar, “Efficient Retiming of Large Circuits,” IEEE Transactions on VLSI Systems, Vol. 6, No. 1, pp. 74 – 83, March 1998.
  62. H. Sathyamurthy, S. S. Sapatnekar, and J. P. Fishburn, “Speeding up Pipelined Circuits through a Combination of Gate Sizing and Clock Skew Optimization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, No. 2, pp. 173 – 182, February 1998.
  63. D. Lehther and S. S. Sapatnekar, “Moment-based techniques for RLC clock tree construction,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 45, No. 1, pp. 69 – 79, January 1998.
  64. S. Ramaswamy, S. Sapatnekar, and P. Banerjee, “A Framework for Exploiting Data and Functional Parallelism on Distributed Memory Multicomputers,” IEEE Transactions on Parallel and Distributed Systems. Vol. 8, No. 11, pp. 1098 – 1116, November 1997
  65. S. S. Sapatnekar and R. B. Deokar, “Utilizing the Retiming-Skew Equivalence in a Practical Algorithm for Retiming Large Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol. 15, No. 10, pp. 1237 – 1248, October 1996.
  66. P. K. Sancheti and S. S. Sapatnekar, “Optimal Design of Macrocells for Low Power and High Speed,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol. 15, No. 9, pp. 1160 – 1166, September 1996.
  67. S. S. Sapatnekar, “Wire Sizing as a Convex Optimization Problem: Exploring the Area Delay Tradeoff,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, No. 8, pp. 1001 – 1011, August 1996.
  68. W. Chuang, S. S. Sapatnekar, and I. N. Hajj, “Timing and Area Optimization for Standard-Cell VLSI Circuit Design,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 14, No. 3, pp. 308 – 320, March 1995.
  69. S. S. Sapatnekar, P. M. Vaidya, and S. M. Kang, “Convexity-based Algorithms for Design Centering,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 13, No. 12, pp. 1536 – 1549, December 1994.
  70. S. S. Sapatnekar, V. B. Rao, P. M. Vaidya, and S. M. Kang, “An Exact Solution to the Transistor Sizing Problem for CMOS Circuits using Convex Optimization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, No. 11, pp. 1621 – 1634, November 1993.
  71. S. S. Sapatnekar and V. B. Rao, “A Transistor Sizing Tool for CMOS Circuits,” Journal of Semicustom IC's, Vol. 8, No. 2, pp. 39 – 44, 1990.

Conference/Workshop Publications

  1. Q. Liu and S. S. Sapatnekar, “Synthesizing a Representative Critical Path for Post-Silicon Delay Prediction,” Proceedings of the ACM International Symposium on Physical Design, pp. 183 – 190, 2009 (Best paper award).
  2. S. S. Sapatnekar, “Addressing Thermal and Power Delivery Bottlenecks in 3D Circuits,” Proceedings of the Asia-South Pacific Design Automation Conference, pp. 423 – 428, 2009.
  3. S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, “Adaptive Techniques for Overcoming Performance Degradation due to Aging in Digital Circuits,” Proceedings of the Asia-South Pacific Design Automation Conference, pp. 284 – 289, 2009.
  4. P. Zhou, K. Sridharan, and S. S. Sapatnekar, “Congestion-Aware Power Grid Optimization for 3D Circuits Using MIM and CMOS Decoupling Capacitors,” Proceedings of the Asia-South Pacific Design Automation Conference, pp. 179 – 184, 2009.
  5. P. Zhou, J. Gu, P. Jain, C. H. Kim, and S. S. Sapatnekar, “Reliable Power Delivery for 3D ICs,” Sematech Workshop on Design and Test Challenges for 3D ICs, 2008.
  6. P.-Y. Yuh, C.-L. Yang, Y.-W. Chang, and S. S. Sapatnekar, “A Progressive-ILP Based Routing Algorithm for Cross-Referencing Biochips,” Proceedings of the ACM/IEEE Design Automation Conference, pp. 284 – 289, 2008.
  7. S. V. Kumar, C. Kashyap, and S. S. Sapatnekar, “A Framework for Block-Based Timing Sensitivity Analysis,” Proceedings of the ACM/IEEE Design Automation Conference, pp. 688 – 693, 2008.
  8. S. V. Kumar, C. Kashyap, and S. S. Sapatnekar, “A Framework for Block-Based Timing Sensitivity Analysis,” ACM Workshop on the Specification and Synthesis of Digital Systems (TAU), 2008.
  9. H. Mogal, H. Qian, K. Bazargan, and S. S. Sapatnekar, “Clustering Based Pruning for Statistical Criticality Computation under Process Variations,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 340 – 343, 2007.
  10. D. Bufistov, J. Cortadella, M. Kishinevsky, and S. S. Sapatnekar, “A General Model for Performance Optimization of Sequential Systems,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 362 – 369, 2007.
  11. Y. Zhan, T. Zhang, and S. S. Sapatnekar, “Module Assignment for Pin-Limited Designs under the Stacked-Vdd Paradigm,”Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 656 – 659, 2007.
  12. S. S. Sapatnekar, “CAD for 3D Circuits: Solutions and Challenges,” Proceedings of the VLSI/ULSI Multilevel Interconnection Conference, pp. 245 – 251, 2007 (Invited).
  13. B. Goplen and S. S. Sapatnekar, “Placement of 3D ICs with Thermal and Interlayer Via Considerations,” Proceedings of the ACM/IEEE Design Automation Conference, pp. 626 – 631, 2007.
  14. J. Gu, S. S. Sapatnekar, and C. H. Kim, “Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift,” Proceedings of the ACM/IEEE Design Automation Conference, pp. 87 – 92, 2007. (Nominated for Best Paper Award).
  15. S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, “NBTI-Aware Synthesis of Digital Circuits,” Proceedings of the ACM/IEEE Design Automation Conference, pp. 370 – 375, 2007.
  16. Q. Liu and S. S. Sapatnekar, “Confidence Scalable Post-Silicon Statistical Delay Prediction under Process Variations,” Proceedings of the ACM/IEEE Design Automation Conference, pp. 497 – 502, 2007.
  17. F. Marques, S. S. Sapatnekar, and A. I. Reis, “DAG Based Library-Free Technology Mapping,” Proceedings of the Great Lakes Symposium on VLSI Systems, pp. 293 – 298, 2007.
  18. Z. Li, C. J. Alpert, S. Quay, S. S. Sapatnekar and W. Shi, “Probabilistic Congestion Prediction with Partial Blockages,” Proceedings of the International Symposium on Quality Electronic Design, 2007.
  19. S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, “An Analytical Model for Negative Bias Temperature Instability,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 493 – 496, 2006.
  20. V. Nookala, D. Lilja, and S. S. Sapatnekar, “Temperature-Aware Floorplanning of Microarchitecture Blocks with IPC-Power Dependence Modeling and Transient Analysis,” Proceedings of the IEEE International Symposium on Low Power Electronics and Design, pp. 298 – 303, 2006.
  21. J. Gu, J. Keane, S. S. Sapatnekar, and C.-H. Kim, “Width Quantization Aware FinFET Circuit Design,” Proceedings of the IEEE Custom Integrated Circuits Conference, 2006.
  22. J. Singh and S. S. Sapatnekar, “Statistical Timing Analysis with Correlated Non-Gaussian Parameters using Independent Component Analysis,” Proceedings of the ACM/IEEE Design Automation Conference, pp. 155 – 160, 2006.
  23. J. Keane, S. S. Sapatnekar, and C. H. Kim, “Subthreshold Logical Effort: A Systematic Framework for Optimal Subthreshold Device Sizing,”Proceedings of the ACM/IEEE Design Automation Conference, pp. 425 – 428, 2006.
  24. S. S. Sapatnekar, “Physical Design Automation Challenges for 3D ICs,” Proceedings of the International Conference on Integrated Circuit Design and Technology, p. 172, 2006 (Invited paper).
  25. H. Qian and S. S. Sapatnekar, “Stochastic Preconditioning for Iterative Linear Equation Solvers,” Ninth Copper Mountain Conference on Iterative Methods, 2006.
  26. V. Nookala, D. J. Lilja, and S. S. Sapatnekar, “Comparing Simulation Techniques for Microarchitecture-Aware Floorplanning,” IEEE International Symposium on Performance Analysis of Systems and Software, pp. 80 – 88, 2006.
  27. S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, “Impact of NBTI on SRAM Read Stability and Design for Reliability,” Proceedings of the International Symposium on Quality Electronic Design pp. 210 – 218, 2006.
  28. Y. Zhan, B. Goplen, and S. S. Sapatnekar, “Electrothermal Analysis and Optimization Techniques for Nanoscale Integrated Circuits,” Proceedings of the Asia-South Pacific Design Automation Conference, pp. 219 – 222, 2006.
  29. T. Zhang, Y. Zhan, and S. S. Sapatnekar, “Temperature-Aware Routing in 3D ICs,” Proceedings of the Asia-South Pacific Design Automation Conference, pp. 309 – 314, 2006.
  30. S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, “Mathematically-Assisted Adaptive Body Bias (ABB) for Temperature Compensation in Gigascale LSI Systems,” Proceedings of the Asia-South Pacific Design Automation Conference, pp. 559 – 564, 2006.
  31. Y. Zhan, Y. Feng, and S. S. Sapatnekar, “A Fixed-die Floorplanning Algorithm Using an Analytical Approach,” Proceedings of the Asia-South Pacific Design Automation Conference, pp. 771 – 776, 2006.
  32. Y. Zhan and S. S. Sapatnekar, “A High Efficiency Full-Chip Thermal Simulation Algorithm,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 634 – 637, 2005.
  33. H. Qian and S. S. Sapatnekar, “A Hybrid Linear Equation Solver and its Application in Quadratic Placement,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 905 – 909, 2005.
  34. F. R. Schneider, R. P. Ribas, S. S. Sapatnekar, and A. I. Reis, “Exact Lower Bound for the Number of Switches in Series to Implement a Combinational Logic Cell,” Proceedings of the IEEE International Conference on Computer Design, pp. 357 – 362, 2005.
  35. B. Goplen, P. Saxena, and S. S. Sapatnekar, “Net Weighting to Reduce Repeater Counts during Placement,” Proceedings of the ACM/IEEE Design Automation Conference, pp. 503 – 508, 2005.
  36. H. Chang and S. S. Sapatnekar, “Full-Chip Analysis of Leakage Power Under Process Variations, Including Spatial Correlations,” Proceedings of the ACM/IEEE Design Automation Conference, pp. 523 – 528, 2005.
  37. J. Singh, Z.-Q. Luo, and S. S. Sapatnekar, “Robust Gate Sizing by Geometric Programming,” Proceedings of the ACM/IEEE Design Automation Conference, pp. 315 – 320, 2005.
  38. V. Nookala, Y. Chen, D. J. Lilja, and S. S. Sapatnekar, “Microarchitecture-aware Floorplanning using a Statistical Design of Experiments Approach,” Proceedings of the ACM/IEEE Design Automation Conference, pp. 579 – 584, 2005.
  39. V. Nookala and S. S. Sapatnekar, “Designing Optimized Pipelined Global Interconnects: Algorithms and Methodology Impact,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 608 – 611, 2005.
  40. S. K. Karandikar and S. S. Sapatnekar, “Fast Estimation of Area-Delay Tradeoffs in Circuit Sizing,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 3575 – 3578, 2005.
  41. F. S. Marques, R. P. Ribas, S. S. Sapatnekar, and A. I. Reis, “A New Approach to the Use of Satisfiability in False Path Detection,” Proceedings of the ACM Great Lakes Symposium on VLSI, pp. 308 – 311, 2005.
  42. J. Singh and S. S. Sapatnekar, “A Fast Algorithm for Power Grid Design,” Proceedings of the ACM International Symposium on Physical Design, pp. 70 – 77, 2005.
  43. R. S. Shelar, P. Saxena, X. Wang, S. S. Sapatnekar, “A Near-optimal Technology Mapping Algorithm Targeting Routing Congestion under Delay Constraints,” Proceedings of the ACM International Symposium on Physical Design, pp. 137 – 144, 2005.
  44. B. Goplen and S. S. Sapatnekar, “Thermal Via Placement in 3D ICs,” Proceedings of the ACM International Symposium on Physical Design, pp. 167 – 174, 2005.
  45. Y. Zhan and S. S. Sapatnekar, “Fast Computation of the Temperature Distribution in VLSI Chips Using the Discrete Cosine Transform and Table Look-up,” Proceedings of the Asia/South Pacific Design Automation Conference, 2005.
  46. T. Zhang and S. S. Sapatnekar, “Buffering Global Interconnects in Structured ASIC Design,” Proceedings of the Asia/South Pacific Design Automation Conference, 2005.
  47. H. Qian, J. Kozhaya, S. R. Nassif, and S. S. Sapatnekar, “A Chip-level Electrostatic Discharge Simulation Strategy,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 315 – 318, 2004.
  48. S. K. Karandikar and S. S. Sapatnekar, “Logical Effort Based Technology Mapping,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 419 – 422, 2004.
  49. C. J. Alpert, J. Hu, S. S. Sapatnekar, and C.-N. Sze, “Accurate Estimation of Global Buffer Delay within a Floorplan,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 706 – 711, 2004.
  50. A. Sultania, D. Sylvester, and S. S. Sapatnekar, “Gate Oxide Leakage Reduction using Transistor and Pin Reordering for Dual Tox Circuits,”
    Proceedings of the IEEE International Conference on Computer Design, pp. 228 – 233, 2004.
  51. T. Zhang and S. S. Sapatnekar, “Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing,” Proceedings of the IEEE International Conference on Computer Design, pp. 93 – 98, 2004.
  52. H. Chang, H. Qian, and S. S. Sapatnekar, “The Certainty of Uncertainty: Randomness in Nanometer Design,” Lecture Notes in Computer Science (Proceedings of PATMOS), E. Macii, V. Paliouras and O. Koufopavlou, ed., Vol. 3254, pp. 36 – 47, Springer, Berlin, Germany, 2004 (Invited Paper).
  53. Y. Zhan, R. Harjani, and S. S. Sapatnekar, “On the Selection of On-Chip Inductors for the Optimal VCO Design,” Proceedings of the IEEE Custom Integrated Circuits Conference, 2004.
  54. V. Nookala and S. S. Sapatnekar, “A Method for Correcting the Functionality of a Wire-Pipelined Circuit,” Proceedings of the ACM/IEEE Design Automation Conference, pp. 570 – 575, 2004 (Nominated for Best Paper Award).
  55. A. Sultania, D. Sylvester, and S. S. Sapatnekar, “Tradeoffs between Gate Oxide Leakage and Delay for Dual Tox Circuits,” Proceedings of the ACM/IEEE Design Automation Conference, pp. 761 – 766, 2004.
  56. J. Singh and S. S. Sapatnekar, “Topology Optimization of Structured Power/Ground Networks,” Proceedings of the ACM International Symposium on Physical Design, pp. 116 – 123, 2004.
  57. H. Qian, S. R. Nassif, and S. S. Sapatnekar, “Early-stage Power Grid Analysis for Uncertain Working Modes,” Proceedings of the ACM International Symposium on Physical Design, pp. 132 – 137, 2004.
  58. R. S. Shelar, S. S. Sapatnekar, P. Saxena, and X. Wang, “A Predictive Distributed Congestion and its Application to Technology Mapping,” Proceedings of the ACM International Symposium on Physical Design, pp. 210 – 217, 2004.
  59. Y. Zhan and S. S. Sapatnekar, “Optimization of Integrated Spiral Inductors Using Sequential Quadratic Programming,” Proceedings of Design and Test in Europe, 2004.
  60. S. K. Karandikar and S. S. Sapatnekar, “Fast Comparison of Circuit Implementations,” Proceedings of Design and Test in Europe, 2004.
  61. C. Alpert, J. Hu, S. Sapatnekar, C-N. Sze, “A Fast Oracle for Interconnect Delay Prediction,”Proceedings of the ACM Workshop on the Specication and Synthesis of Digital Systems (TAU), 2004.
  62. H. Qian and S. S. Sapatnekar, “Hierarchical random-walk algorithms for power grid analysis,” Proceedings of the Asian and South Pacific Design Automation Conference, pp. 499-504, 2004.
  63. S. S. Sapatnekar, “High-performance Power Grids for Nanometer Technology,” Proceedings of the International Conference on VLSI Design, 2004 (Invited paper).
  64. H. Chang and S. S. Sapatnekar, “Statistical Timing Analysis Considering Spatial Correlations Using a Single PERT-like Traversal,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 621 – 625, 2003.
  65. B. Goplen and S. S. Sapatnekar, “Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 86 – 89, 2003.
  66. V. Rajappan and S. S. Sapatnekar, “An Efficient Algorithm for Calculating the Worst-case Delay due to Crosstalk,” Proceedings of the IEEE International Conference on Computer Design, pp. 76 – 81, 2003.
  67. H. Qian, S. R. Nassif and S. S. Sapatnekar, “Random Walks in a Supply Network,” Proceedings of the ACM/IEEE Design Automation Conference, pp. 93 – 98, 2003 (Best paper award).
  68. H. Hu, D. Blaauw, V. Zolotov, K. Gala, M. Zhao, R. Panda, and S. Sapatnekar, “Table Look-up Based Compact Modeling for On-chip Interconnect Timing and Noise Analysis,” Proceedings of the IEEE International Symposium on Circuits and Systems, 2003.
  69. G. Chen and S. S. Sapatnekar, “Partition-Driven Standard Cell Thermal Placement,” Proceedings of the ACM International Symposium on Physical Design, pp. 75 – 80, 2003.
  70. H. Hu, D. T. Blaauw, V. Zolotov, K. Gala, M. Zhao, R. Panda, and S. S. Sapatnekar, “A Precorrected-FFT Method for Simulating On-chip Inductance,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 221 – 227, 2002.
  71. M. Ketkar and S. S. Sapatnekar, “Standby Power Optimization via Transistor Sizing and Dual Threshold Voltage Assignment,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 375 – 378, 2002.
  72. H. Hu and S. S. Sapatnekar, “Efficient PEEC-based Inductance Extraction using Circuit-Aware Techniques,” Proceedings of the IEEE International Conference on Computer Design, pp. 434 – 439, 2002.
  73. H. Su, J. Hu, S. S. Sapatnekar, and S. R. Nassif, “Congestion-driven Codesign of Power and Signal Networks,” Proceedings of the ACM/IEEE Design Automation Conference, pp. 64 – 69, 2002.
  74. R. Shelar and S. S. Sapatnekar, “Efficient Layout Synthesis Algorithm for Pass Transistor Logic Circuits,” Workshop Notes of the International Workshop on Logic and Synthesis, 2002.
  75. H. Su, S. S. Sapatnekar, and S. R. Nassif, “An Algorithm for Optimal Decoupling Capacitor Sizing and Placement for Standard Cell Layouts,” Proceedings of the ACM International Symposium on Physical Design, pp. 68 – 73, 2002.
  76. R. S. Shelar and S. S. Sapatnekar, “An Efficient Algorithm for Low Power Pass Transistor Synthesis,” Proceedings of the International Conference on VLSI Design/Asia-South Pacific Design Automation Conference, pp. 87 – 92, 2002.
  77. H. Su and S. S. Sapatnekar, “Hybrid Structured Clock Network Construction,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 333 – 336, 2001.
  78. R. S. Shelar and S. S. Sapatnekar, “Recursive Bipartitioning of BDDs for Performance Driven Synthesis of Pass Transistor Logic Circuits,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 449 – 452, 2001.
  79. R. S. Shelar and S. S. Sapatnekar, “BDD Decomposition for the Synthesis of High Performance PTL Circuits,” Workshop Notes of the International Workshop on Logic and Synthesis, 2001.
  80. J. Hu and S. S. Sapatnekar, “Performance Driven Global Routing Through Gradual Refinement,” Proceedings of the IEEE International Conference on Computer Design, pp. 481 – 483, 2001.
  81. S. K. Karandikar and S. S. Sapatnekar, “Technology Mapping for SOI Domino Logic Incorporating Solutions for the Parasitic Bipolar Effect,” Proceedings of the ACM/IEEE Design Automation Conference, pp. 377 – 382, 2001.
  82. M. Zhao and S. S. Sapatnekar, “A New Structural Pattern Matching Algorithm for Technology Mapping,” Proceedings of the ACM/IEEE Design Automation Conference, pp. 371 – 376, 2001 (Nominated for best paper award).
  83. C. J. Alpert, J. Hu, S. S. Sapatnekar and P. Villarrubia, “A Practical Methodology for Early Buffer and Wire Resource Allocation,” Proceedings of the ACM/IEEE Design Automation Conference, pp. 189 – 194, 2001 (Best paper award).
  84. H. Hu and S. Sapatnekar, “Circuit-Aware On-Chip Inductance Extraction,” Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 245 – 248, 2001.
  85. C. J. Alpert, G. Gandham, J. Hu, J. L. Neves, S. T. Quay and S. S. Sapatnekar, “Steiner Tree Optimization for Buffers, Blockages and Bays,” Proceedings of the IEEE International Symposium on Circuits and Systems, 2001.
  86. C. J. Alpert, G. Gandham, J. Hu, S. T. Quay, A. J. Sullivan, M. Hrkic, J. Lillis, A. B. Kahng, B. Liu, S. S. Sapatnekar, “Buffered Steiner Trees for Difficult Instances,” Proceedings of the ACM International Symposium on Physical Design, pp. 4 – 9, 2001.
  87. M. Ketkar, S. S. Sapatnekar, and P. Patra, “Convexity-Based Optimization for Power-Delay Tradeoff using Transistor Sizing,” Proceedings of the IEEE/ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp. 52 – 57, 2000.
  88. J. Hu and S. S. Sapatnekar, “A Timing-constrained Algorithm for Simultaneous Routing of Multiple Nets,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 99 – 103, 2000.
  89. H. Su, K. Gala and S. S. Sapatnekar, “Fast Analysis and Optimization of Power/Ground Networks,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 477 – 480, 2000.
  90. M. Ketkar, K. Kasamsetty and S. S. Sapatnekar, “Convex Delay Models for Transistor Sizing,” Proceedings of the ACM/IEEE Design Automation Conference, pp. 655 – 660, 2000.
  91. V. Sundararajan, S. S. Sapatnekar, K. K. Parhi, “MINFLOTRANSIT: Min-Cost Flow Based Transistor Sizing Tool,” Proceedings of the ACM/IEEE Design Automation Conference, pp. 649 – 654, 2000.
  92. M. Zhao, R. V. Panda, S. S. Sapatnekar, T. Edwards, R. Chaudhry, D. Blaauw, “Hierarchical Analysis of Power Distribution Networks,” Proceedings of the ACM/IEEE Design Automation Conference, pp. 150 – 155, 2000.
  93. M. Zhao and S. S. Sapatnekar, “Dual-Monotonic Domino Gate Mapping and Optimal Output Phase Assignment of Domino Logic,” Proceedings of the IEEE International Symposium on Circuits and Systems, 2000.
  94. S. Raman, S. S. Sapatnekar and C. J. Alpert, “Datapath Routing Based on a Decongestion Metric,” Proceedings of the ACM International Symposium on Physical Design, pp. 122 – 127, 2000.
  95. S. S. Sapatnekar, “Capturing the Effect of Crosstalk on Delay,” Proceedings of the 13th International Conference on VLSI Design, pp. 364 – 369, 2000 (Invited Paper) .
  96. S. S. Sapatnekar, “On the Chicken-and-Egg Problem of Determining the Effect of Crosstalk on Delay in Integrated Circuits,” Proceedings of the IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP-99), pp. 245 – 248, 1999 (Invited Paper) .
  97. V. Sundararajan, S. S. Sapatnekar and K. K. Parhi, “MARSH: Minimum Area Retiming with Setup and Hold Constraints,” Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 2 – 6, 1999.
  98. M. Zhao and S. S. Sapatnekar, “Timing-driven Partitioning for Two-Phase Domino and Mixed Static/Domino Implementations,” Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 102 – 105, 1999.
  99. Y. Jiang and S. S. Sapatnekar, “An Integrated Algorithm for Combined Placement and Libraryless Technology Mapping,” Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 107 – 110, 1999.
  100. M. Kuhlmann, S. S. Sapatnekar and K. K. Parhi, “Efficient Crosstalk Estimation,” Proceedings of the IEEE International Conference on Computer Design, pp. 266 – 272, 1999.
  101. J. Pangjun and S. S. Sapatnekar, “Clock Distribution using Multiple Voltages,” Proceedings of the ACM International Symposium on Low Power Electronics and Design, pp. 145-150, 1999.
  102. J. Hu and S. S. Sapatnekar, “FAR-DS: Full-plane AWE Routing with Driver Sizing,” Proceedings of the ACM/IEEE Design Automation Conference, pp. 84 – 89, 1999.
  103. J. Hu and S. S. Sapatnekar, “Simultaneous Buffer Insertion and Non-Hanan Optimization for VLSI Interconnect under a Higher Order AWE Model,” Proceedings of the ACM International Symposium on Physical Design, pp. 133 – 138, 1999.
  104. M. Zhao and S. S. Sapatnekar, “Technology Mapping for Domino Logic,” Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 248 – 251, 1998.
  105. Y. Jiang, S. S. Sapatnekar and C. Bamji, “A Fast Global Gate Collapsing Technique for High Performance Designs Using Static CMOS and Pass Transistor Logic,” Proceedings of the IEEE International Conference on Computer Design, pp. 276 – 281, 1998 (Best paper award).
  106. M. Zhao and S. S. Sapatnekar, “Timing Optimization of Mixed Static and Domino Logic,” Proceedings of the IEEE International Symposium on Circuits and Systems, 1998.
  107. H. Hou and S. S. Sapatnekar, “Routing Tree Topology Construction to Meet Interconnect Timing Constraints,” Proceedings of the ACM International Symposium on Physical Design, pp. 205 – 210, 1998.
  108. Y. Jiang, S. S. Sapatnekar, C. Bamji and J. Kim, “Combined Transistor Sizing with Buffer Insertion for Timing Optimization,” Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 605 – 608, 1998.
  109. N. Maheshwari and S. S. Sapatnekar, “Efficient Minarea Retiming of Large Level-clocked Circuits,” Proceedings of the Design Automation and Test in Europe (DATE) Conference, pp. 840 – 845, 1998.
  110. N. Maheshwari and S. S. Sapatnekar, “Retiming Level-clocked Circuits for Latch Count Minimization,” Proceedings of the ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp. 135 – 140, 1997.
  111. N. Maheshwari and S. S. Sapatnekar, “Minimum Area Retiming with Equivalent Initial States,” Proceedings of the IEEE/ACM International Conference on Computer-aided Design, pp. 216 – 219, 1997.
  112. N. Maheshwari and S. S. Sapatnekar, “An Improved Algorithm for Minimum Area Retiming,” Proceedings of the ACM/IEEE Design Automation Conference, pp. 2 – 6, 1997 (Best paper award).
  113. S. Pilli and S. S. Sapatnekar, “Power Estimation Considering Statistical IC Parameter Variations,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1524 – 1527, 1997.
  114. J. C. Shah, A. A. Younis, S. S. Sapatnekar and M. M. Hassoun, “Symbolic Analysis of Power/Ground Networks using Moment-matching Methods,” Proceedings of the European Conference on Circuit Theory and Design, pp. 1292 – 1297, 1997.
  115. J. Kim, C. Bamji, Y. Jiang and S. S. Sapatnekar, “Concurrent Transistor Sizing and Buffer Insertion by Considering Cost-Delay Tradeoffs,” Proceedings of the International Symposium on Physical Design, pp. 130 – 135, 1997.
  116. D. Lehther and S. S. Sapatnekar, “Clock Tree Synthesis for Multi-Chip Modules,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 53 – 56, 1996.
  117. N. Maheshwari and S. S. Sapatnekar, “A Practical Algorithm for Retiming Level-Clocked Circuits,” Proceedings of the IEEE International Conference on Computer Design, pp. 440 – 445, 1996.
  118. S. S. Sapatnekar, J. Shah and M. M. Hassoun, “Application of Symbolic Analysis to Power and Ground Interconnect Optimization,” Proceedings of the 4th International Workshop on Symbolic Methods and Applications to Circuit Design, 1996.
  119. S. S. Sapatnekar, “Efficient Calculation of All-Pairs Input-to-Output Delays in Synchronous Sequential Circuits,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. IV-520 – IV-523, 1996.
  120. J. C. Shah and S. S. Sapatnekar, “Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs,” Proceedings of VLSI Design-96, pp. 346 – 351, 1996.
  121. S. S. Sapatnekar and W. Chuang, “Power vs. Delay in Gate Sizing: Conflicting Objectives?” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 463 – 466, 1995.
  122. H. Sathyamurthy, S. S. Sapatnekar, and J. P. Fishburn, “Speeding up Pipelined Circuits through a Combination of Gate Sizing and Clock Skew Optimization,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 467 – 470, 1995.
  123. N. Maheshwari and S. S. Sapatnekar, “Gate Size Optimization for Row-based Layouts,” Proceedings of the 38th Midwest Symposium on Circuits and Systems, 1995.
  124. R. B. Deokar and S. S. Sapatnekar, “A Fresh Look at Retiming via Clock Skew Optimization,” Proceedings of the ACM/IEEE Design Automation Conference, pp. 304 – 309, 1995.
  125. P. K. Sancheti and S. S. Sapatnekar, “Layout Optimization Using Arbitrarily High Degree Posynomials,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 53 – 56, 1995.
  126. S. S. Sapatnekar, “RC Interconnect Optimization under the Elmore Delay Model,” Proceedings of the ACM/IEEE Design Automation Conference, pp. 387 – 391, 1994.
  127. P. K. Sancheti and S. S. Sapatnekar, “Interconnect Design Using Convex Optimization,” Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 549 – 552, 1994.
    [No figures in PS file]
  128. R. B. Deokar and S. S. Sapatnekar, “A Graph-theoretic Approach to Clock Skew Optimization,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1.407 – 1.410, 1994.
  129. J. Kim, S. M. Kang, and S. S. Sapatnekar, “High-Performance CMOS Macromodule Layout Synthesis,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 4.179 – 4.182, 1994.
  130. S. Ramaswamy, S. Sapatnekar, and P. Banerjee, “A Convex Programming Approach for Exploiting Data and Functional Parallelism on Distributed Memory Multicomputers,” Proceedings of the International Conference on Parallel Processing, pp. 116 – 125, 1994.
  131. W. Chuang, S. S. Sapatnekar, and I. N. Hajj, “A Unified Algorithm for Gate Sizing and Clock Skew Optimization to Minimize Sequential Circuit Area,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 220 – 223, 1993.
  132. S. S. Sapatnekar, P. M. Vaidya, and S. M. Kang, “Convexity-based Algorithms for Design Centering,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 206 – 209, 1993.
  133. S. S. Sapatnekar, P. M. Vaidya, and S. M. Kang, “Feasible Region Approximation Using Convex Polytopes,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1786 – 1789, 1993. [No figures in pdf file]
  134. W. Chuang, S. S. Sapatnekar, and I. N. Hajj, “Delay and Area Optimization for Discrete Gate Sizes under Double-Sided Timing Constraints,” Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 9.4.1 – 9.4.4, 1993.
  135. S. S. Sapatnekar and V. B. Rao, “A Convex Optimization Approach to Transistor Sizing for CMOS Circuits,” Invited paper at the ORSA/TIMS 34th Joint National Meeting, 1992.
  136. R. W. Thaik, S. S. Sapatnekar, and S. M. Kang, “iCGEN: A CMOS Integrated Circuit Layout Generator,” Proceedings of the International Workshop on Layout Synthesis, 1992.
  137. S. S. Sapatnekar, V. B. Rao, and P. M. Vaidya, “A Convex Optimization Approach to Transistor Sizing for CMOS Circuits,” Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 482 – 485, 1991.
  138. S. S. Sapatnekar and V. B. Rao, “iDEAS: A Delay Estimator and Transistor Sizing Tool for CMOS Circuits,” Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 9.3.1 – 9.3.4, 1990.

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